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MMPF0200 Datasheet(PDF) 4 Page - NXP Semiconductors |
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MMPF0200 Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 114 page  4 NXP Semiconductors PF0200 INTERNAL BLOCK DIAGRAM 2 Internal block diagram Figure 2. PF0200 simplified internal block diagram VIN LICELL SWBSTFB SWBSTIN SWBSTLX O/P Drive SWBST 600 mA Boost SCL SDA VDDIO SW3A/B Single Phase 2500 mA Buck VCOREDIG VCOREREF GNDREF SW1AIN SW1FB SW1ALX SW1BLX SW1A/B Single/Dual 2500 mA Buck VSNVS Li Cell Charger SW2 1500 mA Buck VGEN1 100 mA VGEN1 VIN1 VGEN2 250 mA VGEN2 VGEN3 100 mA VGEN3 VIN2 VGEN4 350 mA VGEN4 VGEN5 100 mA VGEN5 VIN3 VGEN6 200 mA VGEN6 Best of Supply OTP VREFDDR VDDOTP VINREFDDR VHALF VCORE PF0200 CONTROL Clocks 32 kHz and 16 MHz Initialization State Machine I2C Interface Clocks and resets I2C Register map Trim-In-Package O/P Drive O/P Drive SW1BIN SW2FB SW2LX O/P Drive SW2IN SW2IN SW3AIN SW3AFB SW3ALX SW3BLX O/P Drive O/P Drive SW3BIN SW3BFB SW3VSSSNS Supplies Control DVS Control DVS CONTROL Reference Generation Core Control logic GNDREF1 SW1VSSSNS |
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