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MMPF0200 Datasheet(PDF) 10 Page - NXP Semiconductors

Part # MMPF0200
Description  12 channel configurable power management integrated circuit
PDF  114 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0200 Datasheet(HTML) 10 Page - NXP Semiconductors

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NXP Semiconductors
PF0200
GENERAL PRODUCT CHARACTERISTICS
4.2
Thermal characteristics
4.2.1
Power dissipation
During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 4. To optimize the
thermal management and to avoid overheating, the PF0200 provides thermal protection. An internal comparator monitors the die
temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I will be generated when the respective thresholds
specified in Table 5 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register
INTSENSE0.
In the event of excessive power dissipation, thermal protection circuitry will shut down the PF0200. This thermal protection will act above
the thermal protection threshold listed in Table 5. To avoid any unwanted power downs resulting from internal noise, the protection is
debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured
such that this protection is not tripped under normal conditions.
Table 4. Thermal ratings
Symbol
Description (rating)
Min.
Max.
Unit
Thermal ratings
TA
Ambient Operating Temperature Range
PF0200A
PF0200AN
-40
-40
85
105
°C
TJ
Operating Junction Temperature Range
-40
125
°C
(6)
TST
Storage Temperature Range
-65
150
°C
TPPRT
Peak Package Reflow Temperature
–
Note 8
°C
(7)(8)
QFN56 Thermal resistance and package dissipation ratings
RθJA
Junction to Ambient
Natural Convection
Four layer board (2s2p)
Eight layer board (2s6p)
–
–
28
15
°C/W
(9)(10)(11)
RθJMA
Junction to Ambient (@200 ft/min)
Four layer board (2s2p)
–
22
°C/W
(9)(11)
RθJB
Junction to Board
–
10
°C/W
(12)
RΘJCBOTTOM
Junction to Case Bottom
–
1.2
°C/W
(13)
ΨJT
Junction to Package Top
Natural Convection
–
2.0
°C/W
(14)
Notes
6.
Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 5 for
thermal protection features.
7.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
8.
NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), Go to www.nxp.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all
orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
9.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
10.
The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
11.
Per JEDEC JESD51-6 with the board horizontal.
12.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
13.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
14.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-
2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.



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