MMPF0200 datasheet(6/114 Pages) NXP

6 / 114 page

NXP Semiconductors

PF0200

PIN CONNECTIONS

3.2

Pin definitions

Table 2. PF0200 pin definitions

number

Pin name

function

Max rating

Type

Definition

INTB

3.6 V

Digital

Open drain interrupt signal to processor

SDWNB

3.6 V

Digital

Open drain signal to indicate an imminent system shutdown

RESETBMCU

3.6 V

Digital

Open drain reset output to processor. Alternatively can be used as a Power Good

output.

STANDBY

3.6 V

Digital

Standby input signal from processor

ICTEST

7.5 V

Digital/

Analog

Reserved pin. Connect to GND in application.

6SW1FB (4)

3.6 V

Analog

Output voltage feedback for SW1A/B. Route this trace separately from the high-

current path and terminate at the output capacitance.

7SW1AIN (4)

4.8 V

Analog

Input to SW1A regulator. Bypass with at least a 4.7

μF ceramic capacitor and a

0.1

μF decoupling capacitor as close to the pin as possible.

SW1ALX (4)

4.8 V

Analog

Regulator 1A switch node connection

SW1BLX (4)

4.8 V

Analog

Regulator 1B switch node connection

SW1BIN (4)

4.8 V

Analog

Input to SW1B regulator. Bypass with at least a 4.7

μF ceramic capacitor and a

0.1

μF decoupling capacitor as close to the pin as possible.

RSVD1

Reserved

Reserved for pin to pin compatibility. Internally connected. Leave this pin

unconnected.

RSVD2

Reserved

Reserved for pin to pin compatibility. Connect this pin to VIN.

RSVD3

Reserved

Reserved for pin to pin compatibility. Internally connected. Leave this pin

unconnected.

SW1VSSSNS

GND

Ground reference for regulator SW1AB. It is connected externally to GNDREF

through a board ground plane.

GNDREF1

GND

Ground reference for regulator SW2. It is connected externally to GNDREF, via

board ground plane.

VGEN1

2.5 V

Analog

VGEN1 regulator output, Bypass with a 2.2

μF ceramic output capacitor.

VIN1

3.6 V

Analog

VGEN1, 2 input supply. Bypass with a 1.0

μF decoupling capacitor as close to the

pin as possible.

VGEN2

2.5 V

Analog

VGEN2 regulator output, Bypass with a 4.7

μF ceramic output capacitor.

RSVD4

Reserved

Reserved for pin to pin compatibility. Internally connected. Leave this pin

unconnected.

RSVD5

Reserved

Reserved for pin to pin compatibility. Connect this pin to VIN

RSVD6

Reserved

Reserved for pin to pin compatibility. Internally connected. Leave this pin

unconnected.

SW2LX (4)

4.8 V

Analog

Regulator 2 switch node connection

SW2IN (4)

4.8 V

Analog

Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with at least

a 4.7

μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to these pins

as possible.

SW2IN (4)

4.8 V

Analog

SW2FB (4)

3.6 V

Analog

Output voltage feedback for SW2. Route this trace separately from the high-current

path and terminate at the output capacitance.

VGEN3

3.6 V

Analog

VGEN3 regulator output. Bypass with a 2.2

μF ceramic output capacitor.

VIN2

3.6 V

Analog

VGEN3,4 input. Bypass with a 1.0

μF decoupling capacitor as close to the pin as

possible.

MMPF0200 Datasheet(PDF) 6 Page - NXP Semiconductors

MMPF0200 Datasheet(HTML) 6 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL