MMPF0200 datasheet(66/114 Pages) NXP

66 / 114 page

NXP Semiconductors

PF0200

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 82. Register VGEN4CTL - ADDR 0x6F

Name

Bit #

R/W

Default

Description

VGEN4

3:0

R/W

0x80

Sets VGEN4 output voltage.

See Table 77 for all possible configurations.

VGEN4EN

–

0x00

Enables or Disables VGEN4 output

0 = OFF

1 = ON

VGEN4STBY

R/W

0x00

Set VGEN4 output state when in Standby. Refer

to Table 78.

VGEN4LPWR

R/W

0x00

Enable Low Power mode for VGEN4. Refer to

Table 78.

UNUSED

–

0x00

UNUSED

Table 83. Register VGEN5CTL - ADDR 0x70

Name

Bit #

R/W

Default

Description

VGEN5

3:0

R/W

0x80

Sets VGEN5 output voltage.

See Table 77 for all possible configurations.

VGEN5EN

–

0x00

Enables or Disables VGEN5 output

0 = OFF

1 = ON

VGEN5STBY

R/W

0x00

Set VGEN5 output state when in Standby. Refer

to Table 78.

VGEN5LPWR

R/W

0x00

Enable Low Power mode for VGEN5. Refer to

Table 78.

UNUSED

–

0x00

UNUSED

Table 84. Register VGEN6CTL - ADDR 0x71

Name

Bit #

R/W

Default

Description

VGEN6

3:0

R/W

0x80

Sets VGEN6 output voltage.

See Table 77 for all possible configurations.

VGEN6EN

–

0x00

Enables or Disables VGEN6 output

0 = OFF

1 = ON

VGEN6STBY

R/W

0x00

Set VGEN6 output state when in Standby. Refer

to Table 78.

VGEN6LPWR

R/W

0x00

Enable Low Power mode for VGEN6. Refer to

Table 78.

UNUSED

–

0x00

UNUSED

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