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AD5932

Data Sheet

Rev. C | Page 20 of 28

APPLICATIONS INFORMATION

GROUNDING AND LAYOUT

The printed circuit board that houses the AD5932 should be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes that can be easily separated. A minimum

etch technique is generally best for ground planes because it

gives the best shielding. Digital and analog ground planes

should be joined in only one place. If the AD5932 is the only

device requiring an AGND-to-DGND connection, then the

ground planes should be connected at the AGND and DGND

pins of the AD5932. If the AD5932 is in a system where

multiple devices require AGND-to-DGND connections, the

connection should be made at one point only, a star ground

point that should be established as close as possible to the

AD5932.

Avoid running digital lines under the device because these

couple noise onto the die. The analog ground plane should run

under the AD5932 to avoid noise coupling. The power supply

lines to the AD5932 should use as large a track as possible to

provide low impedance paths and reduce the effects of glitches

on the power supply line. Fast switching signals, such as clocks,

should be shielded with digital ground to avoid radiating noise

to other sections of the board. Avoid crossover of digital and

analog signals. Traces on opposite sides of the board should run

at right angles to each other, reducing the effects of feedthrough. A

microstrip technique is by far the best but is not always possible

with a double-sided board. In this technique, the component side

of the board is dedicated to ground planes, while signals are

placed on the other side.

Good decoupling is important. The analog and digital supplies

to the AD5932 are independent and separately pinned out to

minimize coupling between analog and digital sections of the

device. All analog and digital supplies should be decoupled to

AGND and DGND, respectively, with 0.1 µF ceramic capacitors

in parallel with 10 µF tantalum capacitors. To achieve the best

from the decoupling capacitors, they should be placed as close

as possible to the device, ideally right up against the device. In

systems where a common supply is used to drive both the AVDD

and DVDD of the AD5932, it is recommended that the system’s

AVDD supply be used. This supply should have the recom-

mended analog supply decoupling between the AVDD pin of

the AD5932 and AGND and the recommended digital supply

decoupling capacitors between the DVDD pin and DGND.

Interfacing to Microprocessors

The AD5932 has a standard serial interface that allows the part

to interface directly with several microprocessors. The device

uses an external serial clock to write the data/control informa-

tion into the device. The serial clock can have a frequency of

40 MHz maximum. The serial clock can be continuous, or it

can idle high or low between write operations.

When data/control information is being written to the AD5932,

FSYNC is taken low and is held low while the 16 bits of data are

being written into the AD5932. The FSYNC signal frames the

16 bits of information being loaded into the AD5932.

AD5932 TO THE ADSP-BF527 INTERFACE

Figure 34 shows the serial interface between the AD5932 and

the ADSP-BF527. The serial port (SPORT) of the ADSP-BF527

processor must be set up to operate in the DSP serial mode. The

data is clocked out on each rising edge of the serial clock and

clocked into the AD5932 on the SCLK falling edge.

AD59321

ADSP-BF5271

1ADDITIONAL PINS OMITTED FOR CLARITY.

TSF0

DT0PRI

TSCLK0

FSYNC

SDATA

SCLK

Figure 34. ADSP-BF527 to AD5932 Interface

AD5932 TO 68HC11/68L11 INTERFACE

Figure 35 shows the serial interface between the AD5932 and

the 68HC11/68L11 microcontroller. The microcontroller is

configured as the master by setting Bit MSTR in the SPCR to 1,

which provides a serial clock on SCK while the MOSI output

drives the serial data line, SDATA. Because the microcontroller

does not have a dedicated frame sync pin, the FSYNC signal is

derived from a port line (PC7). The set-up conditions for

correct operation of the interface are as follows:

• SCK idles high between write operations (CPOL = 1).

• Data is valid on the SCK falling edge (CPHA = 0).

When data is being transmitted to the AD5932, the FSYNC line is

taken low (PC7). Serial data from the 68HC11/68L11 is transmitted

in 8-bit bytes with only eight falling clock edges occurring in the

transmit cycle. Data is transmitted MSB first. In order to load

data into the AD5932, PC7 is held low after the first eight bits

are transferred and a second serial write operation is performed

to the AD5932. Only after the second eight bits have been

transferred should FSYNC be taken high again.

AD59321

68HC11/68L111

1ADDITIONAL PINS OMITTED FOR CLARITY.

PC7

MOSI

SCK

FSYNC

SDATA

SCLK

Figure 35. 68HC11/68L11 to AD5932 Interface

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