AD8129ARM datasheet(24/28 Pages) AD

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REV. 0

AD8129/AD8130

–24–

The center conductor connects to the positive differential input

of the AD8130. The amplitude of the video signal at this point

is unity, because it is between the two termination resistors. The

AD8130 provides a high impedance to this signal, so it does not

disturb it. A buffered, unity-gain version of the video signal

appears at the output.

Power-Down

The AD8129/AD8130 have a power-down pin that can be used

to lower the quiescent current when the amplifier is not being

used. A logic low level on the PD pin will cause the part to

power down.

Since there is no “Ground” pin on the AD8129/AD8130, there

is no logic reference to interface to standard logic levels. For

this reason, the reference level for the

PD input is +V

S. If the

AD8129/AD8130 are run with +VS = 5 V, there will be direct

compatibility with logic families. However, if +VS is higher

than this, a level-shift circuit will be needed to interface to con-

ventional logic levels. A simple level-shifting circuit that is

compatible with common logic families is presented in Figure 17.

AD8129/

AD8130

+VS

4.99k

LOW=

POWER-DOWN

2N2222

OR EQ

Figure 17. Circuit that Shifts the Logic Level when +VS Is

Not Equal to Approximately 5 V

Extreme Operating Conditions

The AD8129/AD8130 are designed to provide high perfor-

mance over a wide range of supply voltages. However, there are

some extremes of operating conditions that have been observed

to produce non-optimal results. One of these conditions occurs

when the AD8130 is operated at unity gain with low supply

voltage—less than approximately

±4 V.

At unity gain, the output drives FB directly. At supplies of

±VS

less than approximately

±4 V and unity gain, the voltage on FB

can be driven by the output too close to the rail for the circuit to

stay properly biased. This can lead to a parasitic oscillation.

A way to prevent this is to limit the input signal swing with

clamp diodes. Common silicon junction signal diodes like the

1N4148 have a forward bias of approximately 0.7 V when about

1 mA of current flow through them. Two series pairs of such

diodes connected antiparallel across the differential inputs can

be used to clamp the input signal and prevent this condition. It

should be noted that the REF input can also shift the output

signal, so this technique will only work when REF is at ground

or close to it. (See Figure 18.)

AD8130

VOUT

0.1 F10 F

–V

0.1 F

10 F

–VS

+VS

VIN

1N4148

VIN

Figure 18. Clamping Diodes at the Input Limit the Input

Swing Amplitude

Another problem can occur with the AD8129 operating at supply

voltage of greater than or equal to

±12 V. The architecture

causes the supply current to increase as the input differential

voltage increases. If the AD8129 differential inputs are over-

driven too far, excessive current can flow in the device and

potentially cause permanent damage.

A practical means to prevent this from occurring is to differentially

clamp the inputs with a pair of antiparallel Schottky diodes.

(See Figure 19.) These diodes have a lower forward voltage

of approximately 0.4 V. If the differential voltage across the

inputs is restricted to these conditions, no excess current will

be drawn by the AD8129 under these operating conditions.

If the supply voltage is restricted to less than

±11 V, the internal

clamping circuit will limit the differential voltage and excessive

supply current will not be drawn. The external clamp circuit is

not needed.

VIN

AGILENT

HSMS 2822

VOUT

0.1 F10 F

–V

0.1 F

10 F

–VS

+VS

VIN

AD8129

Figure 19. Schottky Diodes Across the Inputs Limits the

Input Differential Voltage

In both circuits, the input series resistors function to limit the

current through the diodes when they are forward-biased. As a

practical matter, these resistors need to be matched to the degree

that the CMRR needs to be preserved at high frequency. These

resistor will have minimal effect on the CMRR at low frequency.

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