Data Sheet

AD5124/AD5144/AD5144A

Rev. B | Page 15 of 36

1

2

3

4

5

6

7

8

9

10

GND

A1

W1

W3

A3

B1

RESET

A2

B3

20

19

18

17

16

15

14

13

12

11

SDA

SCL

W4

B4

W2

B2

A4

ADDR

AD5144A

TOP VIEW

(Not to Scale)

Pin No.

Mnemonic

Description

1

RESET

Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not

2

GND

Ground Pin, Logic Ground Reference.

3

A1

Terminal A of RDAC1. V

4

W1

Wiper Terminal of RDAC1. V

5

B1

Terminal B of RDAC1. V

6

A3

Terminal A of RDAC3. V

7

W3

Wiper Terminal of RDAC3. V

8

B3

Terminal B of RDAC3. V

9

V

SS

Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

10

A2

Terminal A of RDAC2. V

11

W2

Wiper Terminal of RDAC2. V

12

B2

Terminal B of RDAC2. V

13

A4

Terminal A of RDAC4. V

14

W4

Wiper Terminal of RDAC4. V

15

B4

Terminal B of RDAC4. V

16

V

DD

Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

17

V

LOGIC

Logic Power Supply; 1.8 V to V

18

SCL

Serial Clock Line. Data is clocked in at the logic low transition.

19

SDA

Serial Data Input/Output.

20

ADDR

Programmable Address for Multiple Package Decoding.