AD5124 datasheet(16/36 Pages) AD

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AD5124/AD5144/AD5144A

Data Sheet

Rev. B | Page 16 of 36

GND

VDD

VLOGIC

SCL/SCLK

DIS

AD5124/

AD5144

TOP VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE

POTENTIAL OF THE VSS PIN, OR, ALTERNATIVELY, LEAVE

IT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED

THAT THE PAD BE THERMALLY CONNECTED TO A COPPER

PLANE FOR ENHANCED THERMAL PERFORMANCE.

Figure 11. 24-Lead LFCSP Pin Configuration (AD5124/AD5144)

Table 11. 24-Lead LFCSP Pin Function Descriptions (AD5124/AD5144)

Pin No.

Mnemonic

Description

GND

Ground Pin, Logic Ground Reference.

Terminal A of RDAC1. VSS ≤ VA ≤ VDD.

Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.

Terminal B of RDAC1. VSS ≤ VB ≤ VDD.

Terminal A of RDAC3. VSS ≤ VA ≤ VDD.

Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD.

Terminal B of RDAC3. VSS ≤ VB ≤ VDD.

VSS

Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

Terminal A of RDAC2. VSS ≤ VA ≤ VDD.

Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.

Terminal B of RDAC2. VSS ≤ VB ≤ VDD.

Terminal A of RDAC4. VSS ≤ VA ≤ VDD.

Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD.

Terminal B of RDAC4. VSS ≤ VB ≤ VDD.

VDD

Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

VLOGIC

Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

SCL/SCLK

I2C Serial Clock Line (SCL). Data is clocked in at the logic low transition.

SPI Serial Clock Line (SCLK). Data is clocked in at the logic low transition.

DIS

Digital Interface Select (SPI/I2C Select). SPI when DIS = 0 (GND), and I2C when DIS = 1 (VLOGIC). This pin cannot be left

floating.

SDA/SDI

Serial Data Input/Output (SDA), When DIS = 1.

Serial Data Input (SDI), When DIS = 0.

Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM content, except when reloading the

content of the EEPROM into the RDAC register. WP is activated at logic low. If this pin is not used, tie WP to VLOGIC.

ADDR1/SDO

Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1.

Serial Data Output (SDO). Open-drain output, needs an external pull-up resistor, when DIS = 0.

ADDR0/SYNC

Programmable Address (ADDR0) for Multiple Package Decoding, When DIS = 1.

Synchronization Data Input, When DIS = 0. This pin is active low. When SYNC returns high, data is loaded into the input

shift register.

LRDAC

Load RDAC. Transfers the contents of the input registers to their respective RDAC registers when their associated input

registers were previously loaded using Command 2 (see Table 20). This allows simultaneous update of all RDAC

registers. LRDAC is activated at the high-to-low transition. If not used, tie LRDAC to VLOGIC.

RESET

Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If not used, tie RESET to

VLOGIC.

EPAD

Exposed Pad. Connect the exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected.

It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance.

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