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Data Sheet

AD5124/AD5144/AD5144A

Rev. B | Page 25 of 36

I2C SERIAL DATA INTERFACE

The AD5144/AD5144A have 2-wire, I2C-compatible serial

interfaces. These devices can be connected to an I2C bus as a

slave device, under the control of a master device. See Figure 5

for a timing diagram of a typical write sequence.

The AD5144/AD5144A support standard (100 kHz) and fast

(400 kHz) data transfer modes. Support is not provided for

10-bit addressing and general call addressing.

The 2-wire serial bus protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high. The following byte is

the address byte, which consists of the 7-bit slave address

and an R/W bit. The slave device corresponding to the

transmitted address responds by pulling SDA low during

the ninth clock pulse (this is called the acknowledge bit).

At this stage, all other devices on the bus remain idle while

the selected device waits for data to be written to, or read

from, its shift register.

If the R/W bit is set high, the master reads from the slave

device. However, if the R/W bit is set low, the master writes

to the slave device.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

The transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of SCL.

3. When all data bits have been read from or written to, a stop

condition is established. In write mode, the master pulls the

SDA line high during the tenth clock pulse to establish a stop

condition. In read mode, the master issues a no acknowledge

for the ninth clock pulse (that is, the SDA line remains high).

The master then brings the SDA line low before the tenth

clock pulse, and then high again during the tenth clock pulse

to establish a stop condition.

I2C ADDRESS

The AD5144/AD5144A each have two different device address

options available (see Table 12 and Table 13).

Table 12. 20-Lead TSSOP Device Address Selection

ADDR

7-Bit I2C Device Address

LOGIC

0101000

No connect1

0101010

GND

0101011

1 Not available in bipolar mode (V

SS < 0 V) or in low voltage mode (VLOGIC = 1.8 V).

Table 13. 24-Lead LFCSP Device Address Selection

ADDR0 Pin

ADDR1 Pin

7-Bit I2C Device Address

LOGIC

0100000

No connect1

LOGIC

0100010

GND

LOGIC

0100011

LOGIC

No connect1

0101000

No connect1

0101010

GND

No connect1

0101011

LOGIC

GND

0101100

No connect1

GND

0101110

GND

0101111

1 Not available in bipolar mode (V

SS < 0 V) or in low voltage mode (VLOGIC = 1.8 V).

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