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ADF5610 Datasheet(PDF) 39 Page - Analog Devices

Part # ADF5610
Description  Fractional-N PLL with Integrated VCO
PDF  48 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF5610 Datasheet(HTML) 39 Page - Analog Devices

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Preliminary Technical Data
ADF5610
Rev. PrE | Page 39 of 48
AUTOCALIBRATION REGISTER
Table 23. Register 0x0A, VCO Autocalibration Configuration Register (Default 0x002205) – Program to 0x002047
Bit
Type
Name
Width
Default
Description
2:0
R/W
VTUNE resolution
3
5
R divider cycles
0: 1 cycle
1: 2 cycles
2: 4 cycles
…
7: 256 cycles
9:3
R/W
Reserved
7
64d
Program 8d
10
R/W
Force curve
1
0
Program 0
11
R/W
Autocalibration disable
1
0
Program 0 for normal operation using VCO autocalibration
12
R/W
No VSPI trigger
1
0
0: normal operation
1: this bit disables the serial transfers to the VCO subsystem
(via Register 0x05)
14:13
R/W
FSM/VSPI clock select
2
1
These bits set the autocalibration FSM and VSPI clock (50 MHz
maximum)
0: input crystal reference
1: input crystal reference divide by 4
2: input crystal reference divide by 16
3: input crystal reference divide by 32
16:15
R/W
Reserved
2
0
Reserved
PHASE DETECTOR (PD) REGISTER
Table 24. Register 0x0B, PD Register (Default 0x0F8061)
Bit
Type
Name
Width
Default
Description
2:0
R/W
PD_DEL_SEL
3
1
Sets the PD reset path delay (recommended setting is 001).
4:3
R/W
Reserved
2
0
Reserved. Combined separate values shown on 704, using defaults – ok.
5
R/W
PD_UP_EN
1
1
Enables the PD up output.
6
R/W
PD_DN_EN
1
1
Enables the PD down output.
8:7
R/W
CSP mode
2
0
Cycle slip prevention mode. This delay varies by ±10% with temperature and ±12%
with process. Extra current (~8mA) is driven into the loop filter when the phase
error is larger than the following:
0 = disabled.
1 = 5.4 ns.
2 = 14.4 ns.
3 = 24.1 ns.
CSP should only be used with comparison frequencies <= 50MHz, otherwise
disable. Always confirm loop stability when using CSP.
9
R/W
Force CP up
1
0
Forces CP up output to turn on; use for test only.
10
R/W
Force CP
down
1
0
Forces CP down output to turn on; use for test only.
11
R/W
Force CP
Mid-Rail
1
0
Forces CP to Mid-Rail; use for test only.
19:12
R/W
Reserved
13
248d
(0xF8)
Reserved.
[21:20]
R/W
Divider
Pulse Width
2
0
0: Shortest…3: Longest
[23:22]
R/W
Reserved
1
0
Reserved.



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