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S71GL032A Datasheet(PDF) 69 Page - SPANSION |
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S71GL032A Datasheet(HTML) 69 Page - SPANSION |
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69 / 102 page  March 31, 2005 S71GL032A_00_A0 S71GL032A Based MCPs 69 Advance Informatio n Hardware Reset (RESET#) Note:Not 100% tested. Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. Figure 15. Reset Timings Parameter Description All Speed Options Unit JEDEC Std. tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Input Low to Standby Mode (See Note) Min 20 µs tRB RY/BY# Output High to CE#, OE# pin Low Min 0 ns RESET# RY/BY# RY/BY# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP tRB |
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