S71GL032A datasheet(23/102 Pages) SPANSION

23 / 102 page

March 31, 2005 S71GL032A_00_A0

S71GL032A Based MCPs

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Informatio n

Write Buffer

Write Buffer Programming allows the system write to a maximum of 16 in one

programming operation. This results in faster effective programming time than

the standard programming algorithms. See “Write Buffer” for more information.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This

is one of two functions provided by the WP#/ACC or ACC pin, depending on model

number. This function is primarily intended to allow faster manufacturing

throughput at the factory.

If the system asserts VHH on this pin, the device automatically enters the afore-

mentioned Unlock Bypass mode, temporarily unprotects any protected sector

groups, and uses the higher voltage on the pin to reduce the time required for

program operations. The system would use a two-cycle program command se-

quence as required by the Unlock Bypass mode. Removing VHH from the WP#/

ACC or ACC pin, depending on model number, returns the device to normal op-

eration. Note that the WP#/ACC or ACC pin must not be at VHH for operations

other than accelerated programming, or device damage may result. WP# has an

internal pullup; when unconnected, WP# is at VIH.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-

toselect mode. The system can then read autoselect codes from the internal

cycle timings apply in this mode. Refer to the “Autoselect Mode” section on page

31 and “Autoselect Command Sequence” section on page 45 sections for more

information.

Standby Mode

When the system is not reading or writing to the device, it can place the device

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

The device enters the CMOS standby mode when the CE# and RESET# pins are

both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than

VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device

will be in the standby mode, but the standby current will be greater. The device

requires standard access time (tCE) for read access when the device is in either

of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

Refer to the “DC Characteristics” section on page 65 for the standby current

specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-

vice automatically enables this mode when addresses remain stable for tACC +

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-

trol signals. Standard address access timings provide new data when addresses

are changed. While in sleep mode, output data is latched and always available to

S71GL032A Datasheet(PDF) 23 Page - SPANSION

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