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S71GL032A Datasheet(PDF) 97 Page - SPANSION |
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S71GL032A Datasheet(HTML) 97 Page - SPANSION |
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97 / 102 page  March 31, 2005 S71GL032A_00_A0 S71GL032A Based MCPs 97 Advance Informatio n Data Retention Characteristics (4M Version F) Notes: 1. CS1 controlled:CS1# ≥ VCC-0.2V. CS2 controlled: CS2 ≤ 0.2V. 2. Typical values are not 100% tested. Write cycle time tWC 70 - ns Chip select to end of write tCW 60 - ns Address set-up time tAS 0 - ns Address valid to end of write tAW 60 - ns LB#, UB# valid to end of write tBW 60 - ns Write pulse width tWP 50 - ns Write recovery time tWR 0 - ns Write to output high-Z tWHZ 0 20 ns Data to write time overlap tDW 30 - ns Data hold from write time tDH 0 - ns End write to output low-Z tOW 5 - ns Item Symbol Test Condition Min Typ Max Unit VCC for data retention VDR CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V. BYTE# = VSS or VCC 1.5 - 3.3 V Data retention current IDR VCC=3.0V, CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V - 1.0 (Note 2) 10 µA Data retention set-up time tSDR See data retention waveform 0 - - ns Recovery time tRDR tRC - - Parameter List Symbol Speed Bins Units 70ns Min Max |
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