TUSB5052 datasheet(47/84 Pages) TI

47 / 84 page

6–7

6.1.6

DMACSR5: DMA-5 Control and Status Register (P-Port Channel)

This register is used to define the transaction time-out value. In addition, it contains a completion code that reports

any errors or a time-out condition.

TEN

TXFT

PPKT

R/W

R/C

BIT

NAME

RESET

FUNCTION

PPKT

Partial packet condition bit. This bit is set by the DMA and cleared by the MCU (see Table 6–2).

PPKT = 0

No partial-packet condition

PPKT = 1

Partial-packet condition detected. Clears when MCU writes a 1. Writing a 0 has no effect.

TXFT

Transfer Timeout Condition Bit (see Table 6–2 and Table 6–3)

TXFT = 0

DMA stopped transfer without time-out

TXFT = 1

DMA stopped due to transaction time-out. Clears when MCU writes a 1. Writing a 0 has no effect.

6-2

C[4:0]

0000b

This field is used to define the transaction time-out value in 1ms increments. This value is loaded to a down

counter every time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the

counter decrements to zero it sets TXFT = 1 (in DMACSR register) and halts the DMA transfer.

• For OUT transaction: The counter starts counting only when TEN = 1 and EN = 1 (in DMACDR) and the first

byte has been transmitted by the DMA.

• For IN transaction: The counter starts counting only when TEN = 1 and EN = 1 (in DMACDR) and the first byte

has been received by DMA (see Figure 6–1).

00000 = 0 ms time-out

11111 = 31 ms time-out

TEN

Transaction timeout counter enable/disable bit

TEN = 0 Counter is disabled (does

not time out).

TEN = 1 Counter is enabled.

6.2

Bulk Data I/O Using the EDB

The UBM (USB buffer manager) and the DMAC (DMA controller) access the EDB to fetch buffer parameters for IN

and OUT transactions (IN and OUT are with respect to host). In this discussion, it is assumed that (a) the MCU

initialized the EDBs, (b) DMA-continuous mode is being used, (c) double buffering is being used, and (d) the X/Y

toggle is controlled by the UBM.

NOTE:The IN and OUT transfers apply to UART and P-port transactions (SPP, EPP and ECP

modes).

IN Transaction (TUSB5152 to Host):

MCU initializes the IEDB (64-byte packet, and double-buffering is used) and the following DMA registers:

•

DMACSR: Defines the transaction time-out value.

•

DMACDR: Defines the IEDB being used and the DMA mode of operation (continuous-mode). Once this

DMA transfers data from a device (UART or P-port) to the X-buffer. When a block of 64-bytes is transferred,

the DMA updates the byte-count and sets NAK = 0 in IEDB (indicating to the UBM that the X-buffer is ready

to be transferred to host). The UBM starts X-buffer transfer to host using the byte-count value in IEDB and

toggles the X/Y-bit. The DMA continues transferring data from a device to Y-buffer. At the end of the block

transfer, the DMA updates the byte-count and sets NAK = 0 in IEDB (indicating to the UBM that the Y-buffer

is ready to be transferred to host). The DMA continues the transfer from the device to host, alternating

between X and Y buffers without MCU intervention.

Transfer termination: As mentioned, the DMA/UBM continues the data transfer, alternating between the X

and Y buffers. Termination of the transfer can happen under the following conditions:

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