TUSB5052 datasheet(57/84 Pages) TI

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7–9

7.1.12 XON[2-1]: Xon Register (2 Registers)

These registers contain a value that is compared to the received data stream. Detection of a match interrupts the MCU

(only if the interrupt enable bit is set). This value is also used for Xon transmission.

R/W

BIT

NAME

RESET

FUNCTION

7–0

D[7:0]

0000

Xon value to be compared to the incoming data stream.

7.1.13 XOFF[2-1]: Xoff Register (2 Registers)

These registers contain a value that is compared to the received data stream. Detection of a match halts the DMA

transfer, and interrupts the MCU (only if the interrupt enable bit is set). This value is also used for Xoff transmission.

R/W

BIT

NAME

RESET

FUNCTION

7–0

D[7:0]

0000

Xon value to be compared to the incoming data stream.

7.1.14 MASK[2-1]: UART Interrupt-Mask Register (2 Registers)

These registers control the UARTs interrupt sources.

RSV

TRIE

SIE

MIE

R/O

R/W

BIT

NAME

RESET

FUNCTION

MIE

This bit controls the UART-modem interrupt.

MIE = 0

Modem-interrupt is disabled.

MIE = 1

Modem-interrupt is enabled.

SIE

This bit controls the UART-status interrupt.

SIE = 0

Status-interrupt is disabled.

SIE = 1

Status-interrupt is enabled.

TRIE

This bit controls the UART-TxE/RxF interrupts.

TRIE = 0 TxE/RxF interrupts are disabled.

TRIE = 1 TxE/RxF interrupts are enabled.

7–3

RSV

Reserved = 0

7.2

UARTs Data Transfer

Figure 7–2 illustrates the data transfer between the UARTs and the host using the DMA controller and the USB buffer

manager (UBM). A buffer of 512 bytes is reserved for buffering all UART channels (2 transmit and 2 receive buffers).

Each UART channel has 64-bytes of double-buffer space (X- and Y-buffer). When the DMA writes to the X-buffer,

the UBM reads from the Y-buffer. Similarly, when the DMA reads from the X-buffer, the UBM writes to the Y-buffer.

The DMA channel is configured to operate in the continuous mode (by setting DMACDR[CNT] = 1). Once the MCU

enables the DMA, data transfer toggles between the UMB and the DMA without MCU intervention. See section 6.2

for DMA transfer-termination condition.

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