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TUSB5052 Datasheet(PDF) 5 Page - Texas Instruments |
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TUSB5052 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 84 page  v 8 IEEE 1284 Parallel-Post 8–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 1284 Registers 8–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 PPCNT: P-Port Counter Register 8–2 . . . . . . . . . . . . . . . . . . . . . 8.1.2 PPMCR: P-Port Mode Control Register 8–2 . . . . . . . . . . . . . . . . 8.1.3 PPIMSK: P-Port Interrupt Mask Register 8–3 . . . . . . . . . . . . . . . 8.1.4 PPSTA: P-Port Status Register 8–3 . . . . . . . . . . . . . . . . . . . . . . . 8.1.5 PPCTL: P-Port Control Register 8–4 . . . . . . . . . . . . . . . . . . . . . . 8.1.6 PPADR: EPP/ECP Address Register 8–4 . . . . . . . . . . . . . . . . . . 8.1.7 PPDAT: P-Port Data Register 8–5 . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Mode-1 (SPP): Bidirectional Centronics Mode 8–5 . . . . . . . . . . . . . . . . . . . 8.2.1 MCU Output Sequence 8–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 MCU Input Sequence 8–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 DMA Input Sequence 8–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Mode-2/3: EPP and ECP Modes 8–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 DMA Output Sequence 8–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 DMA Input Sequence 8–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Host IN/OUT Transaction From/To P-Port 8–7 . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 Host IN Transaction 8–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Host OUT Transaction 8–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interrupts 9–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 8052 Interrupt and Status Registers 9–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 8052 Standard Interrupt Enable Register 9–1 . . . . . . . . . . . . . . . 9.1.2 Additional Interrupt Sources 9–1 . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.3 IEPINT: Input End-point Interrupt Request Register 9–2 . . . . . . 9.1.4 OEPINT: Output End-point Interrupt Request Register 9–2 . . . 9.1.5 VECINT: Vector Interrupt Register 9–2 . . . . . . . . . . . . . . . . . . . . . 9.1.6 Logical Interrupt Connection Diagram 9–4 . . . . . . . . . . . . . . . . . 10 I2C Port 10–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 I2C Registers 10–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 I2CSTA: I2C Status and Control Register 10–1 . . . . . . . . . . . . . . 10.1.2 I2CADR: I2C Address Register 10–2 . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 I2CDAI: I2C Data-Input Register 10–2 . . . . . . . . . . . . . . . . . . . . . . 10.1.4 I2CDAO: I2C Data-Output Register 10–2 . . . . . . . . . . . . . . . . . . . 10.2 Random-Read Operation 10–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Device Address + EPROM [High-Byte] 10–2 . . . . . . . . . . . . . . . . 10.2.2 EPROM [Low-byte] 10–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Current-Address Read Operation 10–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Sequential-Read Operation 10–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Device Address 10–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 N-Byte Read (31 Bytes) 10–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 Last-Byte Read (Byte 32) 10–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Byte-Write Operation 10–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.1 Device Address + EPROM [High-Byte] 10–4 . . . . . . . . . . . . . . . . 10.5.2 EPROM [Low-Byte] 10–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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