AD9152-EBZ datasheet(44/103 Pages) AD

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AD9152

Data Sheet

Rev. B | Page 44 of 103

Configuration Parameters

The AD9152 modes refer to the link configuration parameters

for L, K, M, N, NP, S, and F. Table 44 provides the description

and addresses for these settings.

Table 44. Configuration Parameters

JESD204B

Setting

Description

Address

L − 1

Number of lanes − 1.

0x453[4:0]

F − 1

Number of ((octets per frame) per

lane) − 1.

0x454[7:0]

K − 1

Number of frames per multiframe − 1.

0x455[4:0]

M − 1

Number of converters − 1.

0x456[7:0]

N − 1

Converter bit resolution − 1.

0x457[4:0]

NP − 1

Bit packing per sample − 1.

0x458[4:0]

S − 1

Number of ((samples per converter)

per frame) − 1.

0x459[4:0]

High density format. Set to 1 if F = 1.

Leave at 0 if F ≠ 1.

0x45A[7]

F parameter, in ((octets per frame) per

lane).

0x476[7:0]

DID

Device ID. Match the device ID sent

by the transmitter.

0x450[7:0]

BID

Bank ID. Match the bank ID sent by

the transmitter.

0x451[3:0]

LID0

Lane ID for Lane 0. Match the lane ID

sent by the transmitter on Logical

Lane 0.

0x452[4:0]

JESDV

JESD version. Match the version sent

by the transmitter (0x0 = JESD204A,

0x1 = JESD204B).

0x459[7:5]

1 The values that need to be written in Register 0x454 and Register 0x476 are

different, F − 1 and F, respectively.

Data Flow Through the JESD204B Receiver

The link configuration parameters determine how the serial bits

on the JESD204B receiver interface are deframed and passed on

to the DACs as data samples. Figure 54 shows a detailed flow of

the data through the various hardware blocks for Mode 4 (L = 4,

M = 2, S = 1, F = 1). Simplified flow diagrams for all other modes

are shown in Figure 54 through Figure 59.

Single Link Configuration

The AD9152 uses the settings contained in Table 43. Mode 4 to

Mode 10, except Mode 8, can be used for single link operation.

Checking Proper Configuration

As a convenience, the AD9152 provides quick configuration

checks. Register 0x030, Bit 5 is high if an illegal LMFC_DELAY_0

value is used. Register 0x030, Bit 3 is high if an unsupported

combination of L, M, F, or S is used. Register 0x030, Bit 2 is high

if an illegal K character is used. Register 0x030, Bit 1 is high if an

illegal SUBCLASSV is used.

Deskewing and Enabling Logical Lanes

After proper configuration, the logical lanes must be deskewed and

enabled to capture data.

Set Bit x in Register 0x46C to 1 to deskew Logical Lane x and to 0 if

that logical lane is not being used. Then, set Bit x in Register 0x47D

to 1 to enable Logical Lane x and to 0 if that logical lane is not

being used.

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