AD9152-EBZ datasheet(2/103 Pages) AD

2 / 103 page

AD9152

Data Sheet

Rev. B | Page 2 of 103

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications..................................................................................... 5

DC Specifications ......................................................................... 5

Digital Specifications ................................................................... 6

Maximum DAC Update Rate Speed Specifications by

Supply............................................................................................. 7

JESD204B Serial Interface Speed Specifications ...................... 7

SYSREF± to DAC Clock Timing Specifications....................... 8

Digital Input Data Timing Specifications ................................. 8

Latency Variation Specifications ................................................ 9

JESD204B Interface Electrical Specifications ........................... 9

AC Specifications........................................................................ 10

Absolute Maximum Ratings.......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions........................... 12

Terminology .................................................................................... 14

Typical Performance Characteristics ........................................... 15

Theory of Operation ...................................................................... 20

Serial Port Operation ..................................................................... 21

Data Format ................................................................................ 21

Serial Port Pin Descriptions...................................................... 21

Serial Port Options ..................................................................... 21

Chip Information............................................................................ 23

Device Setup Guide ........................................................................ 24

Overview...................................................................................... 24

Step 1: Start Up the DAC........................................................... 24

Step 2: Digital Datapath............................................................. 25

Step 3: Transport Layer.............................................................. 25

Step 4: Physical Layer................................................................. 26

Step 5: Data Link Layer.............................................................. 26

Step 6: Optional Error Monitoring .......................................... 26

Step 7: Optional Features........................................................... 26

DAC PLL Setup........................................................................... 27

Interpolation ............................................................................... 27

JESD204B Setup ......................................................................... 27

SERDES Clocks Setup................................................................ 28

Equalization Mode Setup .......................................................... 28

Link Latency Setup..................................................................... 28

Crossbar Setup............................................................................ 30

JESD204B Serial Data Interface.................................................... 31

JESD204B Overview .................................................................. 31

Physical Layer ............................................................................. 32

Data Link Layer .......................................................................... 35

Transport Layer .......................................................................... 43

JESD204B Test Modes ............................................................... 51

JESD204B Error Monitoring..................................................... 52

Digital Datapath ............................................................................. 54

Data Format ................................................................................ 54

Interpolation Filters ................................................................... 54

Digital Modulation..................................................................... 55

NCO Alignment ......................................................................... 56

Inverse Sinc ................................................................................. 57

Programmable FIR Filter (PFIR) ............................................. 57

Digital Gain, Phase Adjust, DC Offset, and Coarse Group

Delay ............................................................................................ 57

Downstream Protection ............................................................ 59

Datapath PRBS ........................................................................... 61

DC Test Mode............................................................................. 62

Interrupt Request Operation ........................................................ 63

Interrupt Service Routine.......................................................... 63

DAC Input Clock Configurations ................................................ 64

Driving the DACCLK± AND REFCLK± Inputs ................... 64

Condition Specific Register Writes.......................................... 64

Starting the PLL.......................................................................... 65

Analog Outputs............................................................................... 67

Transmit DAC Operation.......................................................... 67

Temperature Sensor ....................................................................... 68

Example Start-Up Sequence.......................................................... 69

Step 1: Start Up the DAC........................................................... 69

Step 2: Digital Datapath............................................................. 70

Step 3: Transport Layer.............................................................. 70

Step 4: Physical Layer................................................................. 70

Step 5: Data Link Layer.............................................................. 70

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