AD9152-EBZ datasheet(96/103 Pages) AD

96 / 103 page

AD9152

Data Sheet

Rev. B | Page 96 of 103

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

ERRCNT_LOBITS

count from the selected lane.

0x31B

PHY_PRBS_TEST_

ERRCNT_MIDBITS

[7:0]

PHY_PRBS_ERR_

CNT[15:8]

Bits[15:8] of the 24-bit reported PHY BERT error

count from the selected lane.

0x0

0x31C

PHY_PRBS_TEST_

ERRCNT_HIBITS

[7:0]

PHY_PRBS_ERR_

CNT[23:16]

Bits[23:16] of the 24-bit reported PHY BERT error

count from the selected lane.

0x0

0x31

PHY_PRBS_TEST_

STATUS

[7:4]

RESERVED

Reserved.

0x0

[3:0]

PHY_PRBS_PASS

PHY PRBS test pass/fail.

0xF

Bit x corresponds to PHY PRBS pass/fail for

Physical Lane x. The bit is set to 1 while the error

count for Physical Lane x is less than

PHY_PRBS_THRESHOLD.

0x32C

SHORT_TPL_TEST_0

[7:6]

RESERVED

Reserved.

0x0

R/W

[5:4]

SHORT_TPL_SP_SEL

Short transport layer sample select. Selects which

sample to check from the DAC selected via

Bits[3:2].

0x0

R/W

x Sample x.

[3:2]

SHORT_TPL_DAC_SEL

Short transport layer test DAC select. Selects

which DAC to sample.

0x0

R/W

x Sample from DAC x.

SHORT_TPL_TEST_RESET

Short transport layer test reset. Resets the result

of short transport layer test.

0x0

R/W

0 Not reset.

1 Reset.

SHORT_TPL_TEST_EN

Short transport layer test enable. See the Subclass 0

section for details on how to perform this test.

0x0

R/W

0 Disable.

1 Enable.

0x32

SHORT_TPL_TEST_1

[7:0]

SHORT_TPL_REF_SP_LSB

Short transport layer test reference, sample LSB.

This is the lower eight bits of the expected DAC

sample. It is used to compare with the received

DAC sample at the output of the JESD204B

receiver.

0x0

R/W

0x32E

SHORT_TPL_TEST_2

[7:0]

SHORT_TPL_REF_SP_MSB

Short transport layer test reference, sample MSB.

This is the upper eight bits of the expected DAC

sample. It is used to compare with the received

DAC sample at the output of the JESD204B

receiver.

0x0

R/W

0x32F

SHORT_TPL_TEST_3

[7:1]

RESERVED

Reserved.

0x0

SHORT_TPL_FAIL

Short transport layer test fail. This bit shows

whether the selected DAC sample matches the

reference sample. If they match, it is a test pass,

otherwise it is a test fail.

0x0

0 Test pass.

1 Test fail.

0x334

JESD_BIT_INVERSE_CTRL

[7:4]

RESERVED

Reserved.

0x0

R/W

[3:0]

JESD_BIT_INVERSE

Logical lane invert. Set Bit x high to invert the

JESD204B deserialized data on Logical Lane x.

0x0

R/W

0x400

DID_REG

[7:0]

DID_RD

Device identification number. Link information

received on Lane 0 as specified in Section 8.3 of

JESD204B.

0x0

0x401

BID_REG

[7:4]

ADJCNT_RD

Adjustment resolution to DAC LMFC. Link

information received on Lane 0 as specified in

Section 8.3 of JESD204B.

0x0

[3:0]

BID_RD

Bank identification: extension to DID. Link

information received on Lane 0 as specified in

Section 8.3 of JESD204B.

0x0

0x402

LID0_REG

RESERVED

Reserved.

0x0

ADJDIR_RD

Direction to adjust DAC LMFC. Link information

received on Lane 0 as specified in Section 8.3 of

JESD204B. Must be 0.

0x0

PHADJ_RD

Phase adjustment request to DAC. Link information

received on Lane 0 as specified in Section 8.3 of

JESD204B. Must be 0.

0x0

AD9152-EBZ Datasheet(PDF) 96 Page - Analog Devices

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