AD9152-EBZ datasheet(27/103 Pages) AD

27 / 103 page

Data Sheet

AD9152

Rev. B | Page 27 of 103

DAC PLL SETUP

This section explains how to select appropriate LODivMode,

RefDivMode, and BCount values in the Device Setup Guide

section. These parameters depend on the desired DAC clock

frequency (fDAC) and DAC reference clock frequency (fREF).

When using the DAC PLL, the reference clock signal is applied

to the REFCLK± differential pins (Pin 3 and Pin 4).

Table 24. DAC PLL LODivMode Settings

DAC Frequency Range (MHz)

LO_DIV_MODE,

1500 to 2250

750 to 1500

420 to 750

Table 25. DAC PLL RefDivMode Settings

DAC PLL Reference

Frequency (fREF) (MHz)

Divide by

Factor

(RefDivFactor)

REF_DIV_MODE,

Bits[2:0]

80 to 160

160 to 320

320 to 640

640 to 1000

The VCO frequency (fVCO) is related to the DAC clock frequency

according to the following equation:

fVCO = fDAC × 2LODivMode + 1

where 6 GHz ≤ fVCO ≤ 12 GHz.

BCount must be between 6 and 127 and is calculated based on

fDAC and fREF as follows:

BCount = floor((fDAC)/(2 × fREF/RefDivFactor))

where RefDivFactor = 2RefDivMode (see Table 25).

Finally, to finish configuring the DAC PLL, set the VCO control

registers up as described in Table 73 based on the VCO

frequency (fVCO).

For more information on the DAC PLL, see the DAC Input

Clock Configurations section.

INTERPOLATION

The transmit path can use zero to three cascaded interpolation

filters, which each provide a 2× increase in output data rate and

a low-pass function. Table 26 shows the different interpolation

modes and the respective usable bandwidth along with the

maximum fDATA rate attainable when the power supply is 1.2 V.

Table 26. Interpolation Modes and Their Usable Bandwidth

Interpolation

Mode

InterpMode

Usable

Bandwidth

Maximum fDATA

(MHz)

1× (bypass)

0x00

fDATA

1238 (JESD204B

limited)

2×

0x01

0.4 × fDATA

1125

4×

0x02

0.4 × fDATA

562.5

8×

0x03

0.4 × fDATA

281.25

The usable bandwidth is defined for 1×, 2×, 4×, and 8× modes

as the frequency band over which the filters have a pass-band

ripple of less than ±0.001 dB and an image rejection of greater

than 85 dB. For more information, see the Interpolation Filters

section.

JESD204B SETUP

This section explains how to select a JESD204B operating mode

for a desired application. This in turn defines appropriate values

for CheckSumMode, UnusedLanes, DualLink, CurrentLink,

Scrambling, L, F, K, M, N, Np, Subclass, S, HD, Lane0Checksum,

and Lanes needed for the Device Setup Guide section.

Note that DualLink, Scrambling, L, F, K, M, N, Np, S, HD, and

Subclass must be set the same on the transmit side.

For a summary of how a JESD204B system works and what each

parameter means, see the JESD204B Serial Data Interface section.

Available Operating Modes

Table 27. JESD204B Operating Modes (Single Link)

Mode

Parameter

M (Converter Count)

L (Lane Count)

S ((Samples per Converter) per Frame)

F ((Octets per Frame) per Lane)

For a particular application, the number of converters to use (M)

and the fDATA (DataRate) are known. The LaneRate and number

of lanes (L) can be traded off as follows:

DataRate = (DACRate)/(InterpolationFactor)

LaneRate = (20 × DataRate × M)/L

where LaneRate is between 1.44 Gbps and 12.38 Gbps at 1.3 V.

Octets per frame per lane (F) and samples per convertor per

frame (S) define how the data is packed. If F = 1, the high density

setting must be set to one (HD = 1). Otherwise, set HD = 0.

Converter resolution and bits per sample (N and Np) must both

be set to 16. Frames per multiframe (K) must be set to 32 for

Mode 4 and Mode 9. Other modes may use either K = 16 or

K = 32.

Scrambling

Scrambling is a feature that makes the spectrum of the link data

independent. This avoids spectral peaking and provides some

protection against data dependent errors caused by frequency

selective effects in the electrical interface. Set to 1 if scrambling

is being used, or to 0 if it is not.

Subclass

Subclass determines whether the latency of the device is

deterministic, meaning it requires an external synchronization

signal. See the Subclass Setup section for more information.

CurrentLink

Set CurrentLink to 0 to configure Link 0.

AD9152-EBZ Datasheet(PDF) 27 Page - Analog Devices

AD9152-EBZ Datasheet(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL