AD9152-EBZ datasheet(58/103 Pages) AD

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AD9152

Data Sheet

Rev. B | Page 58 of 103

Phase Adjust

Ordinarily, the I and Q channels of each DAC pair have an

angle of 90° between them. The phase adjust feature changes the

angle between the I and Q channels, which can help balance the

phase into a modulator.

−14 ≤ DegreesAdjust < 14

IQPhaseAdj = (DegreesAdjust/14) × 212

where IQPhaseAdj is a 13-bit, twos complement number.

The phase adjust is set as shown in Table 61.

Table 61. I/Q Phase Adjustment Registers

Addr.

Value

Description

0x111[4]

PHASE_ADJ_ENABLE

Set to 1 to enable phase

adjust

0x11C

PHASE_ADJ[7:0]

LSB phase adjust code

0x11D

PHASE_ADJ[12:8]

MSB phase adjust code

DC Offset

The dc offset feature individually offsets the data into the I or Q

DACs. This can be used to cancel LO leakage.

The offset is programmed individually for I and Q as a 16-bit

twos complement number in LSBs, plus a 5-bit, twos complement

number in sixteenths of an LSB, as shown in Table 62.

−215 ≤ LSBsOffset < 215 − 1

−16/16 LSB ≤ SixteenthsOffset ≤ 15/16 LSB

Table 62. DC Offset Registers

Addr.

Value

Description

0x135[0]

DC_OFFSET_ON

Set to 1 to enable dc offset

0x136

LSB_OFFSET_I[7:0]

I DAC LSB dc offset code

0x137

LSB_OFFSET_I[15:8]

I DAC MSB dc offset code

0x138

LSB_OFFSET_Q[7:0]

Q DAC LSB dc offset code

0x139

LSB_OFFSET_Q[15:8]

Q DAC MSB dc offset code

0x13A

SIXTEENTH_OFFSET_I

I DAC sub-LSB dc offset code

0x13B

SIXTEENTH_OFFSET_Q Q DAC sub-LSB dc offset code

Figure 65 shows how the DAC output currents vary as a

function of the LSBsOffset value. With the digital inputs fixed at

midscale (0x0000, twos complement data format), Figure 65

shows the nominal current of the positive node of the DAC

output, IIOUT+/IQOUT+, as the DAC offset value is swept from 0 to

65,535. Because IOUT+/QOUT+ and IOUT−/QOUT− are

complementary current outputs, the sum of IIOUT+ and IIOUT− or

IQOUT+ and IQOUT− is always 20 mA.

0x00000

0x40000

0x80000

0xC0000

0xFFFFF

DAC OFFSET VALUE

Figure 65. DAC Output Currents vs. DAC Offset Value

Coarse Group Delay Adjustment

Coarse group delay is programmed in Register 0x047. The

range of the delay is −4 DAC clock periods to +3 DAC clock

periods and the resolution is 1/2 DAC clock period. Coarse

group delay can be used for DPD loop delay adjustment.

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