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AD5675 Datasheet(PDF) 5 Page - Analog Devices |
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AD5675 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 27 page  Data Sheet AD5675 Rev. C | Page 5 of 27 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 1.62 V ≤ VLOGIC ≤ 5.5 V, all specifications TA = −40°C to +125°C, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments Output Voltage Settling Time1 5 8 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse1 1.4 nV-sec 1 LSB change around major carry (gain = 1) Digital Feedthrough1 0.13 nV-sec Digital Crosstalk1 0.1 nV-sec Analog Crosstalk1 −0.25 nV-sec Gain = 1 −1.3 nV-sec Gain = 2 DAC-to-DAC Crosstalk1 −2.0 nV-sec Gain = 2 Total Harmonic Distortion (THD)1, 2 −80 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz Output Noise Spectral Density (NSD)1 80 nV/√Hz DAC code = midscale, bandwidth = 10 kHz, gain = 1 and 2 Output Noise 6 µV p-p 0.1 Hz to 10 Hz, gain = 1 Signal-to-Noise Ratio (SNR) 90 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz Spurious-Free Dynamic Range (SFDR) 83 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz Signal-to-Noise-and-Distortion Ratio (SINAD) 80 dB TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz 1 See the Terminology section. 2 Digitally generated sine wave (fOUT) at 1 kHz. TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, all specifications −40°C to +125°C, unless otherwise noted. Table 4. Parameter1 Min Max Unit Description t1 2.5 µs SCL cycle time t2 0.6 µs tHIGH, SCL high time t3 1.3 µs tLOW, SCL low time t4 0.6 µs tHD,STA, start/repeated start hold time t5 100 ns tSU,DAT, data setup time t62 0 0.9 µs tHD,DAT, data hold time t7 0.6 µs tSU,STA, repeated start setup time t8 0.6 µs tSU,STO, stop condition setup time t9 1.3 µs tBUF, bus free time between a stop condition and a start condition t103 0 300 ns tR, rise time of SCL and SDA when receiving t113 20 + 0.1CB ns tF, fall time of SCL and SDA when transmitting/receiving t12 20 ns LDAC pulse width t13 400 ns SCL rising edge to LDAC rising edge t14 8 ns RESET minimum pulse width low, 1.62 V ≤ VLOGIC ≤ 2.7 V 10 ns RESET minimum pulse width low, 2.7 V ≤ VLOGIC ≤ 5.5 V t15 90 ns RESET activation time, 1.62 V ≤ VLOGIC ≤ 2.7 V 90 ns RESET activation time, 2.7 V ≤ VLOGIC ≤ 5.5 V tSP4 0 50 ns Pulse width of suppressed spike CB4 400 pF Capacitive load for each bus line 1 See Figure 2 and Figure 3. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the minimum VIH of the SCL signal) to bridge the undefined region of the SCL falling edge. 3 tR and tF are measured from 0.3 × VDD to 0.7 × VDD. 4 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. |
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