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AD5675 Datasheet(PDF) 18 Page - Analog Devices |
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AD5675 Datasheet(HTML) 18 Page - Analog Devices |
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18 / 27 page ![]() AD5675 Data Sheet Rev. C | Page 18 of 27 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The AD5675 is an octal, 16-bit, serial input, voltage output DAC. The AD5675 operates from a supply voltage of 2.7 V to 5.5 V. Data is written to the AD5675 in a 24-bit word format via a 2-wire serial interface. The AD5675 incorporates a power-on reset circuit to ensure that the DAC output powers up to a known output state. The device also has a software power-down mode that reduces the typical current consumption to 1 µA. TRANSFER FUNCTION The gain of the output amplifier is set to ×1 or ×2 using the gain select pin (GAIN). When the gain select pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. When the gain select pin is tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF. DAC ARCHITECTURE The AD5675 implements a segmented string DAC architecture with an internal output buffer. Figure 40 shows the internal block diagram. INPUT REGISTER DAC REGISTER RESISTOR STRING REF (+) VREF GND REF (–) VOUTx GAIN (GAIN = 1 OR 2) Figure 40. Single DAC Channel Architecture Block Diagram The simplified segmented resistor string DAC structure is shown in Figure 41. The code loaded to the DAC register determines the node on the string where the voltage is tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches and connecting the string to the amplifier. Because each resistance in the string has the same value, R, the string DAC is guaranteed monotonic. R R R R R TO OUTPUT AMPLIFIER VREF Figure 41. Resistor String Structure Output Amplifier The output buffer amplifier generates rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. The actual range depends on the value of VREF, the GAIN pin, the offset error, and the gain error. The GAIN pin selects the gain of the output. If the GAIN pin is tied to GND, all eight outputs have a gain of 1, and the output range is 0 V to VREF. If the GAIN pin is tied to VLOGIC, all eight outputs have a gain of 2, and the output range is 0 V to 2 × VREF. This amplifier can drive a load of 1 kΩ in parallel with 10 nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to ¾ scale settling time of 5 µs. |
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