AD5675 datasheet(19/27 Pages) AD

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Data Sheet

AD5675

Rev. C | Page 19 of 27

SERIAL INTERFACE

The AD5675 uses a 2-wire, I2C-compatible serial interface. The

device can be connected to an I2C bus as a slave device under

the control of the master devices. The AD5675 supports

standard (100 kHz) and fast (400 kHz) data transfer modes.

Support is not provided for 10-bit addressing and general call

addressing.

Input Shift Register

The input shift register of the AD5675 is 24 bits wide. Data

is loaded MSB first (DB23), and the first four bits are the

command bits, C3 to C0 (see Table 9), followed by the 4-bit

DAC address bits, A3 to A0 (see Table 10), and finally, the 16-

bit data-word.

The data-word comprises a 16-bit input code (see Figure 42).

These data bits are transferred to the input register on the

24 falling edges of SCL.

Commands execute on individual DAC channels, combined DAC

channels, or on all DACs, depending on the address bits selected.

Table 9. Command Definitions

Command

Description

No operation

Write to Input Register n (where n = 0 to 7,

depending on the DAC selected from the

address bits in Table 10, dependent

on LDAC)

Update DAC Register n with the contents

of Input Register n

Write to and update DAC Channel n

Power down/power up the DAC

Hardware LDAC mask register

Software reset (power-on reset)

Gain setup register (LFCSP package only)

Reserved

Set up the readback register (readback

enable)

Update all channels of the input register

simultaneously with the input data

Update all channels of the DAC register

and input register simultaneously with

the input data

Reserved

…

Reserved

Table 10. Address Commands

Channel Address, Bits[3:0]

Selected DAC Channel

DAC 0

DAC 1

DAC 2

DAC 3

DAC 4

DAC 5

DAC 6

DAC 7

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

D15

D14

D13

D12

D11

D10

COMMAND

DAC ADDRESS

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

DATA LOW BYTE

Figure 42. Input Shift Register Content

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