AD9858 datasheet(5/32 Pages) AD

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AD9858

Rev. A | Page 5 of 32

Parameter

Temp

Test

Level

Min

Typ

Max

Unit

TIMING CHARACTERISTICS

Serial Control Bus

Maximum Frequency

Full

MHz

Minimum Clock Pulse Width Low (tPWL)

Full

5.5

Minimum Clock Pulse Width High (tPWH)

Full

Maximum Clock Rise/Fall Time

Full

Minimum Data Setup Time (tDS)

Full

Mimimum Data Hold Time (tDH)

Full

Maximum Data Valid Time (tDV)

Full

Parallel Control Bus

WR Minimum Low Time

Full

WR Minimum High Time

Full

WR Minimum Period

Full

Address to WR Setup (TASU)

Full

Address to WR Setup (TAHU)

Full

Data to WR Setup (TDSU)

Full

3.5

Data to WR Hold (TDHU)

Full

Miscellaneous Timing Specifications

REFCLK to SYNCLK

Full

2.5

FUD to SYNCLK Setup Time

Full

FUD to SYNCLK Hold Time

Full

REFCLK to SYNCLK Delay

Full

2.5

FUD Rising Edge to Frequency Change

Single Tone Mode

25°C

sysclk

cycles

Linear Sweep Mode

25°C

sysclk

cycles

FUD Rising Edge to Phase Offset Change

25°C

sysclk

cycles

1 The reference clock input is configured to accept a differential or single-ended sine wave input or a 3 V CMOS-level pulse input.

2 REFCLK input is internally dc biased. AC coupling should be used.

3 Reference clock frequency is selected to ensure second harmonic is out of the bandwidth of interest.

4 PD inputs sent @ 400 MHz, with divide-by-4 enabled.

5 The charge pump current is programmable in eight discrete steps, minimum value assumes current sharing.

6 For 0.75 V < VCP < CPVDD – 0.75 V.

7 These differential inputs are internally dc biased. AC coupling should be used.

8 The charge pump supply voltage can range from 4.75 V to 5.25 V.

9 Output interface is differential open collector.

10 For 1 dB output compression; input power measured at 50 Ω.

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