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AD9858

Rev. A | Page 26 of 32

CFR<19>: Clear Phase Accumulator Bit

When CFR<19> = 1, the phase accumulator is synchronously

cleared and is held clear until CFR<19> is returned to a Logic 0

state (default).

CFR<18>: Not Used.

CFR<17>: PLL Fast-Lock Enable Bit

When CFR<17> = 0 (default), the PLL’s fast-lock algorithm is

disabled.

When CFR<17> = 1, the PLL’s fast-lock algorithm is active.

CFR<16>

This bit allows the user to control whether or not the PLL’s fast-

locking algorithm uses the tuning word value to determine

whether or not to enter fast-locking mode.

When CFR<16> = 0 (default), the PLL’s fast-locking algorithm

considers the relationship between the programmed frequency

tuning word and the instantaneous frequency as part of the

locking process.

When CFR<16> = 1, the PLL’s fast-locking algorithm does not

use the frequency tuning word as part of the locking process.

CFR<15>: Frequency Sweep Enable Bit

When CFR<15> = 0 (default), the device is in the single-

tone mode.

When CFR<15> = 1, the device is in the frequency-

sweep mode.

CFR<14>: Sine/Cosine Select Bit

When CFR<14> = 0 (default), the angle-to-amplitude

conversion logic employs a cosine function.

When CFR<14> = 1, the angle-to-amplitude conversion logic

employs a sine function.

CFR<13>: Charge Pump Current Offset Bit

When CFR<13> = 0 (default), the charge pump operates with

normal current settings.

When CFR<13> = 1, the charge pump operates with offset

current settings (see charge pump description).

CFR<12:11>: Phase Detector Reference

Input Frequency Divider Ratio

These bits set the phase detector divide value per Table 10.

Table 10.

CFR<12:11>

Phase Detector

Divider Ratio (N)

Notes

00b

Default Value

01b

1xb

LSB Ignored

CFR<10>: Charge Pump Polarity Select Bit

When CFR<10> = 0 (default), the charge pump is set up for

operation with a ground-referenced VCO. In this mode, the

charge pump sources current when the frequency at PDIN is less

than the frequency at DIVIN. It sinks current when the opposite

is true.

When CFR<10> = 1, the charge pump is set up for a supply-

referenced VCO. In this mode, the charge pump’s source/sink

operation is opposite that for a ground-referenced VCO.

CFR<9:8>: Phase Detector Feedback

Input Frequency Divider Ratio

These bits set the phase detector divide value per Table 11.

Table 11.

CFR<9:8>

Phase Detector Divider

Ratio (M)

Notes

00b

Default value

01b

1xb

LSB ignored

CFR<7>: Not Used

CFR<6>: Disable Bit for the 2 GHz REFCLK Divider

When CFR<6> = 0 (default), the REFCLK divide-by-2 function

is not bypassed. REFCLK input can be up to 2 GHz.

When CFR<6> = 1, the REFCLK divide-by-2 function is

disabled. REFCLK input must be no more than 1 GHz.

CFR<5>: SYNCLK Disable Bit

When CFR<5> = 0 (default), the SYNCLK pin is active.

When CFR<5> = 1, the SYNCLK pin assumes a static Logic 0

state (disabled). In this state, the pin drive logic is shut down to

keep noise generated by the digital circuitry at a minimum.

However, the synchronization circuitry remains active

(internally) to maintain normal device timing.

CFR<4:2>: Power-Down Bits

Active high (Logic 1) powers down the respective function.

Writing a Logic 1 to all three bits causes the device to enter full-

sleep mode.

CFR<4> is used to shut down the analog mixer stage

(default = 1).

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