AD9858 datasheet(15/32 Pages) AD

15 / 32 page

AD9858

Rev. A | Page 15 of 32

THEORY OF OPERATION

OVERVIEW

The AD9858 direct digital synthesizer (DDS) is a flexible device

that can address a wide range of applications. The device

consists of an NCO with a 32-bit phase accumulator, 14-bit

phase offset adjustment, a power efficient DDS core, and a one

giga-samples per second (1 GSPS) 10-bit digital-to-analog

converter. The AD9858 incorporates additional capabilities for

automated frequency sweeping. The device also offers an analog

mixer capable of operating at 2 GHz, a phase-frequency

detector (PFD), and a programmable charge pump (CP) with

advanced fast-lock capability. These RF building blocks can be

used for various frequency synthesis loops or as needed in

system design.

The AD9858 can directly generate frequencies up to 400+ MHz

when driven at a 1 GHz internal clock speed. This clock can be

derived from an external clock source of up to 2 GHz by using

the on-chip divide-by-2 feature. The on-chip mixer and

PFD/CP make possible a variety of synthesizer configurations

capable of generating frequencies in the 1 GHz to 2 GHz range

or higher.

The AD9858 offers the advantages of a DDS with the additional

flexibility to work in concert with analog frequency synthesis

techniques (PLL, mixing) to generate precision frequency

signals with high frequency resolution, fast frequency hopping,

fast settling time, and automated frequency sweeping

capabilities.

Writing data to its on-chip digital registers that control all

operations of the device easily configures the AD9858. The

AD9858 offers a choice of both serial and parallel ports for

controlling the device. Four user profiles can be selected by a

pair of external pins. These profiles allow independent setting

of the frequency tuning word and the phase offset adjustment

word for each of four selectable configurations.

The AD9858 can be programmed to operate in single-tone

mode or in frequency-sweeping mode. To save on power

consumption, there is also a programmable full-sleep mode,

during which most of the device is powered down to reduce

current flow.

The operation of a DDS is described in detail in a tutorial

available from Analog Devices at www.analog.com/dds.

COMPONENT BLOCKS

DDS Core

The DDS core generates the numeric values that represent a

sinusoid in the digital domain. Depending on the operating

mode of the DDS, this sinusoid may be changed in frequency,

phase, or perhaps modulated by an information carrying signal.

The frequency of the output signal is determined by a user-

programmed frequency tuning word (FTW). The relation of the

output frequency of the device to the system clock (SYSCLK) is

determined by the following equation:

()

SYSCLK

FTW

where for the AD9858, N = 32.

For a more detailed explanation of a DDS core, consult the DDS

tutorial at www.analog.com/dds.

DAC Output

The AD9858 incorporates an integrated 10-bit current output

DAC. Two complementary outputs provide a combined full-

scale output current (IOUT). Differential outputs reduce the

amount of common-mode noise that might be present at the

DAC output, offering the advantage of an increased signal-to-

noise ratio. The full-scale current is controlled by means of an

external resistor (RSET) connected between the DACISET pin

and analog ground. The full-scale current is proportional to the

resistor value as follows:

OUT

SET

The maximum full-scale output current of the combined DAC

outputs is 40 mA, but limiting the output to 20 mA provides the

best spurious-free dynamic range (SFDR) performance. The

DAC output compliance range is (AVDD – 1.5 V) to

(AVDD + 0.5 V). Voltages developed beyond this range cause

excessive DAC distortion and could potentially damage the

DAC output circuitry. Proper attention should be paid to the

load termination to keep the output voltage within this

compliance range. When terminating the differential outputs

into a transformer, the center tap should be attached to AVDD.

PLL Frequency Synthesizer

The PLL frequency synthesizer is a group of independent

synthesis blocks, designed to be used with the DDS to expand

the range of synthesis applications. These blocks are a digital

phase-frequency detector (PFD) that drives a charge pump

(CP). The charge pump incorporates fast-locking logic,

described below. Based on system requirements, the user

supplies an external loop filter and one or more VCOs. A high

speed analog mixer is included for translation synthesis loops.

Using the different blocks in the PLL frequency synthesizer in

conjunction with the DDS, the user can create translation loops

(also known as offset loops), fractional divider loops, as well as

traditional PLL loops to multiply the output of the DDS in

frequency.

AD9858 Datasheet(PDF) 15 Page - Analog Devices

AD9858 Datasheet(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL