AD9858 datasheet(23/32 Pages) AD

23 / 32 page

AD9858

Rev. A | Page 23 of 32

Serial Programming Mode

In serial programming mode, the I/O port uses a chip select pin

(CS), a serial clock pin (SCLK), an I/O reset pin (IORESET),

and either 1 or 2 serial data pins (SDIO and/or SDO). The

number of serial data pins used depends on the configuration

of the I/O port; i.e., whether it has been configured for 2-wire or

3-wire serial operation as defined by the control function

bidirectional serial data pin. In 3-wire mode, the SDIO pin

operates only as a serial data input pin, and the SDO pin acts as

the serial output. The maximum rate of SCLK is 10 MHz;

however, during read operation, the 10 MHz rate is not

guaranteed.

The serial port is an SPI compatible serial interface and its

operation is virtually identical to that of the AD9852/AD9854.

Serial port communication occurs in two phases. Phase 1 is an

instruction cycle consisting of an 8-bit word. The MSB of the

instruction byte flags the ensuing operation as a read or write

operation. The 6 LSBs define the serial address of the target

format is given in Table 5.

Table 5.

D7 (MSB)

DO (LSB)

1: Read

0: Write

Phase 2 of a serial port communication contains the data to be

routed to/from the addressed register. The number of bytes

transferred during Phase 2 depends on the length of the target

serial register address be transferred.

Both phases of a serial port communication require the serial

data clock (SCLK) to be operating. When writing to the device,

serial bits are transferred on the rising edge of SCLK. When

reading from the device, serial output bits are transferred on the

falling edge of SCLK. The bit order for both phases of a serial

port communication is selectable via the control function

The CS pin serves as a chip select control line. When CS is at a

Logic 1 state, the SDO and SDIO pins are disabled (forced into a

high impedance state). Only when the CS pin is at a Logic 0

state are the SDO and SDIO pins active. This allows multiple

devices to exist on a single serial bus. If multiple devices are

connected to the same serial bus, then communication with a

single device is accomplished by setting CS to a Logic 0 state on

the target device, but to a Logic 1 state on all other devices. In

this way, serial communication occurs only between the

controller and the target device.

In the case where I/O synchronization is lost between the

AD9858 and the external controller, the IORESET pin provides

a means to re-establish synchronization without initializing the

entire device. Asserting the active high IORESET pin resets the

serial port state machine. This terminates the current I/O

operation and puts the device into a state in which the next

eight SCLK pulses are expected to be the instruction byte of the

next I/O transfer. Note that any information previously written

to the memory registers during the last valid communication

cycle prior to loss of synchronization remains intact.

The registers are listed in Table 6. The serial address and parallel

address numbers associated with each of the registers are shown

in hexadecimal format. Angle brackets <> are used to reference

specific bits or ranges of bits. For example, <3> designates Bit 3,

while <7:3> designates the range of bits from 7 down to 3,

inclusive.

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