AD9858 datasheet(25/32 Pages) AD

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AD9858

Rev. A | Page 25 of 32

Control Function Register (CFR)

The CFR is comprised of four bytes located in parallel addresses

0x03 to 0x00. The CFR is used to control the various functions,

features, and modes of the AD9858. The functionality of each

bit is detailed below. Note that the register bits are identified

according to their serial register bit locations beginning with the

most significant bit.

CFR<31:30>: Frequency-Detect Mode Charge Pump Current

These bits are used to set the scale factor for the frequency-

detect mode charge pump output current per Table 7. The

charge pump delivers the scaled output current when the

control logic forces the charge pump into its frequency detect

operating mode. The charge pump’s baseline output current

(ICP0) is determined by the external CPISET resistor and is

given by

1.24/CPISE

ICP0 =

The recommended nominal value of the CPISET resistor is

2.4 kΩ, which yields a baseline current of 500 µA.

Table 7.

CFR<31:30>

Frequency-Detect

Charge Pump

Scale Value

Notes

00b

IOUT = 0 (Default)

01b

IOUT = 20 × ICP0

10b

IOUT = 40 × ICP0

11b

IOUT = 60 × ICP0

CFR<29:27>: Final Closed-Loop Mode

Charge Pump Output Current

These bits are used to set the scale factor for the final closed-

loop mode charge pump output current per Table 8. The charge

pump delivers the scaled output current when the control logic

forces the charge pump into its final closed-loop mode.

Table 8.

CFR<29:27>

Final Closed-Loop

CP Scale Value

Notes

0xxb

IOUT = 0 (Default)

100b

IOUT = ICP0

101b

IOUT = 2 × ICP0

110b

IOUT = 3 × ICP0

111b

IOUT = 4 × ICP0

CFR<26:24>: Wide Closed-Loop Charge Pump

Output Current

These bits are used to set the scale factor for the wide closed-

loop charge pump output current, see Table 9. The charge pump

delivers the scaled output current when the control logic forces

the charge pump into its wide closed-loop operating mode.

Table 9.

CFR<26:24>

Wide Closed-Loop

CP Scale Value

Notes

000b

IOUT = 0 (Default)

001b

IOUT = 2 × ICP0

010b

IOUT = 4 × ICP0

011b

IOUT = 6 × ICP0

100b

IOUT = 8 × ICP0

101b

IOUT = 10 × ICP0

110b

IOUT = 12 × ICP0

111b

IOUT = 14 × ICP0

CFR<23>: AutoClear Frequency Accumulator Bit

When CFR<23> = 0 (default), a new delta frequency word is

applied to the input of the accumulator and added to the

currently stored value.

When CFR<23> = 1, this bit automatically synchronously clears

(loads zeros into) the frequency accumulator for one cycle upon

reception of the FUD sequence indicator.

CFR<22>: AutoClear Phase Accumulator Bit

When CFR<22> = 0 (default), a new frequency tuning word is

applied to the input of the phase accumulator and added to the

currently stored value.

When CFR<22> = 1, this bit automatically synchronously clears

(loads zeros into) the phase accumulator for one cycle upon

reception of the FUD sequence indicator.

CFR<21>: Load Delta-Frequency Timer

When CFR<21> = 1 (default), the contents of the delta

frequency ramp rate word are loaded into the ramp rate timer

(down counter) upon detection of a FUD sequence.

When CFR<21> = 0, the contents of the delta frequency ramp

rate word are loaded into the ramp rate timer upon timeout

with no regard to the state of the FUD sequence indicator (i.e.,

the FUD sequence indicator is ignored).

CFR<20>: Clear Frequency Accumulator Bit

When CFR<20> = 1, the frequency accumulator is

synchronously cleared and is held clear until CFR<20> is

returned to a Logic 0 state (default).

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