AD9858 datasheet(30/32 Pages) AD

30 / 32 page

AD9858

Rev. A | Page 30 of 32

EVALUATION BOARDS

The AD9858 has three different evaluation board designs. The

first design is the traditional DDS evaluation board. In this

design, the DDS is clocked and the output is taken directly from

the DAC. The analog mixer and PLL blocks are made available

for separate evaluation.

The second design is a fractional-divide loop. This evaluation

board was designed to incorporate the DDS, the phase-detector,

and the charge pump. In this application, the DDS is used in a

PLL loop. Unlike a fixed divider used in traditional PLL loops,

the output signal is divided and fed back to the phase detector

by the DDS. To do this, the output signal of the PLL loop is fed

to the DDS as REFCLK. The DDS is programmed to match the

reference input frequency. Because the DDS output frequency

can take on 232 potential values between 0 Hz and one half of

the PLL loop output frequency, this enables frequency

resolution on the order of 470 MHz, assuming a PLL loop

output frequency of 2 GHz.

The third design is a translation loop or offset loop. In this

design, the RF mixer is incorporated into the feedback path of

the loop. This allows direct up-conversion to the transmission

frequency.

The three evaluation boards have separate schematics, BOMS,

and instructions. See www.analog.com/dds for more

information.

Table 13.

Part Number

Description

AD9858PCB

AD9858 Frequency Synthesizer Board

AD9858FDPCB

AD9858 Fractional-Divide Loop Frequency

Synthesizer Board

AD9858TLPCB

AD9858 Translation Loop Frequency

Synthesizer Board

AD9858 Datasheet(PDF) 30 Page - Analog Devices