LTC2633

22

2633fc

For more information www.linear.com/LTC2633

Please refer to http://www.linear.com/product/LTC2633#packaging for the most recent package drawings.

Board Layout

ThePCboardshouldhaveseparateareasfortheanalogand

digital sections of the circuit. A single, solid ground plane

should be used, with analog and digital signals carefully

routed over separate areas of the plane. This keeps digital

signals away from sensitive analog signals and minimizes

the interaction between digital ground currents and the

analog section of the ground plane. The resistance from

the LTC2633 GND pin to the ground plane should be as

low as possible. Resistance here will add directly to the

effective DC output impedance of the device (typically

0.1Ω). Note that the LTC2633 is no more susceptible to

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

analog ground, digital ground, and power ground. When

the LTC2633 is sinking large currents, this current flows

out the ground pin and directly to the power ground trace

without affecting the analog ground plane voltage.

It is sometimes necessary to interrupt the ground plane

to confine digital ground currents to the digital portion of

the plane. When doing this, make the gap in the plane only

as long as it needs to be to serve its purpose and ensure

that no traces cross over the gap.

OPERATION

PACKAGE DESCRIPTION

1.50 – 1.75

(NOTE 4)

2.80 BSC

0.22 – 0.36

8 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20

(NOTE 3)

TS8 TSOT-23 0710 REV A

2.90 BSC

(NOTE 4)

0.65 BSC

1.95 BSC

0.80 – 0.90

1.00 MAX

0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.40

MAX

0.65

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.4 MIN

2.62 REF

1.22 REF

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637 Rev A)