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Oki Semiconductor

MSM13Q0000/14Q0000

0.35 µm Sea of Gates Arrays

DESCRIPTION

Oki’s 0.3 5 µm ASIC products deliver ultra-high performance and high density at low power dissipation.

The MSM13Q0000/14Q0000 series devices (referred to as “MSM13Q/14Q”) are implemented with the

industry-standard Cell-Based Array (CBA) architecture in a Sea-of-Gates (SOG) structure. Built in a

0.35 µm drawn CMOS technology (with an L-Effective of 0.27 µm), these SOG devices are available in

three layers (MSM13Q) and four layers (MSM14Q) of metal. The semiconductor process is adapted from

Oki’s production-proven 64-Mbit DRAM manufacturing process.

The MSM13Q/14Q Series contains 6 arrays each, offering over 1 million raw gates and 352 I/O pads. Up

to 66% and 90% of the raw gates can be used for the 3-layer and 4-layer arrays, respectively. Oki’s 0.35

µm family is optimized for 3-V core operation with optimized 3-V I/O buffers and 5-V tolerant 3-V buff-

ers. These SOG products are designed to fit the most popular plastic quad flat packs (QFPs), thin QFPs

(TQFPs) , and plastic ball grid array (PBGA) packages.

The MSM13Q/14Q Series uses the popular CBA architecture from Silicon Architects of Synopsys which

mixes two types of cells (8-transistor compute cells and 4-transistor drive cells) on the same die to deliver

high gate density and high drives. The CBA is supported by a rich macro library, optimized for synthesis.

Memory blocks are efficiently created by Oki’s memory compilers to generate single- and dual-port

RAM’s in high-density and low-power configurations with synchronous RAM options.

As such, the MSM13Q/14Q series is well suited to memory-intensive designs with high production vol-

umes approaching the real estate and cost savings of standard cells. At the same time, its SOG architec-

ture allows rapid prototyping turnaround times. Thus, Oki’s MSM13Q/14Q family offers the best of two

worlds: quick prototyping of a gate array and low production cost of a standard cell.

Oki’s 0.35 µm ASIC products are supported by leading-edge CAD tools including a synthesis-linked

floorplanner, motive static timing analyzer, and H-clock tree methodology. They are further supported

by specialized macrocells including phase-locked loop (PLL), pseudo-emitter coupled logic (PECL),

peripheral component interconnect (PCI), universal synchronous receiver/transmitter (UART) cells, and

ARM7TDMI RISC cores.

FEATURES

• 0.35 µm drawn 3- and 4-layer metal CMOS

• Optimized 3.3-V core

• Optimized 3-V I/O and 3-V I/O that is 5-V

tolerant

• CBA SOG architecture

• Over 1.0M raw gates and 352 pads

state, and 1- to 24-mA options

• Slew-rate-controlled outputs for low-radiated

noise

• H-clock tree cells which reduce the maximum

skew for clock signals

• User-configurable single and dual-port;

synchronous or asynchronous memories

• Specialized macrocells including PLL, PECL,

PCI, UART, and ARM7TDMI

• Floorplanning for front-end simulation, back-

end layout controls, and link to synthesis

• Joint Test Action Group (JTAG) boundary scan

and scan-path ATPG

• Support for popular CAE systems, including

Cadence, IKOS, Mentor Graphics, Synopsys,

Viewlogic, and Zycad