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10

Oki Semiconductor

Design Process

The following figure illustrates the overall IC design process and shows the three main interface points

between external design houses and Oki ASIC Application Engineering.

Floorplanning

Floorplanning

Scan Insertion (Optional)

( Zycad)

Schematics

Test Vectors

VHDL/HDL Description

Test Vector Conversion

Netlist Conversion

(EDIF 200)

Pre-Layout Simulation

(Cadence Verilog)

Layout

Automatic Test

Pattern Generation

(Synopsys Test Compiler)

Verification

(Cadence DRACULA)

Post-Layout Simulation

(Cadence Verilog)

Manufacturing

Prototype

Test Program

Conversion

Level 2

CAE Front-End

Oki Interface

[1] Oki’s Circuit Data Check (CDC) program verifies logic design rules.

[2] Oki’s Link to Synthesis Floorplanning (LSF) toolset transfers post-floorplanning timing for resynthesis.

[3] Oki’s Test Data Check (TDC) program verifies test vector rules.

[4] Oki’s Test Pattern Language (TPL).

[5] Alternate Customer-Oki design interfaces available in addition to standard level 2.

[6] Standard design process includes fault simulation.

Gate-Level Simulation

Floorplanning

Synthesis

Figure 5. Oki’s Design Process