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ADV7310KST Datasheet(PDF) 19 Page - Analog Devices |
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ADV7310KST Datasheet(HTML) 19 Page - Analog Devices |
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19 / 84 page  REV. A ADV7310/ADV7311 –19– SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values Reserved 00 Zero must be written to these bits 20h 0Disabled 1 Enabled 0x11h, Bit 2 must also be enabled 0Disable Programmable RGB matrix 1 Enable Programmable RGB matrix Sync on RGB 1 0No Sync 1 Sync on all RGB outputs 0RGB component outputs 1YUV component outputs 0No Sync output 1Output SD Syncs on HSYNC output, VSYNC output, BLANK output HD Sync 0 No Sync output 1Output HD Syncs on HSYNC output, VSYNC output, BLANK output 03h RGB Matrix 0 xx LSB for GY 03h RGB Matrix 1 x x LSB for RV F0h xx LSB for BU xx LSB for GV xx LSB for GU 05h RGB Matrix 2 x x x x x x x x Bit 9–2 for GY 4Eh 06h RGB Matrix 3 x x x x x x x x Bit 9–2 for GU 0Eh 07h RGB Matrix 4 x x x x x x x x Bit 9–2 for GV 24h 08h RGB Matrix 5 x x x x x x x x Bit 9–2 for BU 92h 09h RGB Matrix 6 x x x x x x x x Bit 9–2 for RV 7Ch 0Ah DAC A, B, C Output Level 2 Positive Gain to DAC Output Voltage 000 0 00 000% 00h 00 00 00 01 +0.018% 00 00 00 10 0.036% ……… 00 11 11 11 +7.382% 01 00 00 00 +7.5% Negative Gain to DAC Output Voltage 11 00 00 00 –7.5% 11 00 00 01 –7.382% 10 00 00 10 –7.364% … ……. 11 11 11 11 –0.018% 0Bh DAC D, E, F Output Level Positive Gain to DAC Output Voltage 000 0 00 000% 00h 00 00 00 01 +0.018% 00 00 00 10 0.036% ……… 00 11 11 11 +7.382% 01 00 00 00 +7.5% Negative Gain to DAC Output Voltage 11 00 00 00 –7.5% 11 00 00 01 –7.382% 10 00 00 10 –7.364% … ……. 11 11 11 11 –0.018% 0Ch Reserved 00h 0Dh Reserved 00h 0Eh Reserved 00h 0Fh Reserved 00h SD Sync RGB/YUV Output 04h RGB Matrix Test Pattern Black Bar 02h Mode Register 0 NOTES 1For more detail, refer to Appendix 7. 2For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section. |
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