MSM548262-80JS datasheet(28/37 Pages) OKI

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Write Mask Data/Data Input and Output: DQ1 - DQ8

In conventional write-per bit mode, the DQ pins function as mask data at the falling edge of RAS.

Data is written only to high DQ pins. Data on low DQ pins is masked and internal data is retained.

After that, they function as input/output pins similar to a standard DRAM.

Serial Clock: SC

SC is a main serial cycle control input signal. All operations of the SAM port are synchronized

with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In

a serial read cycle, the output data becomes valid on the SDQ pins after the maximum specified

serial access time tSCA from the rising edge of SC.

In a serial write cycle, data on SDQ pins at the rising edge of SC are fetched into the SAM register.

Serial Enable:

The SE is a serial access enable control and serial read/write control signal. In a serial read cycle,

SE is used as an output control. In a serial write cycle, SE is used as a write enable control. When

SE is "high", serial access is disabled. However, the serial address pointer location is still

incremented when SC is clocked even when SE is "high".

Special Function Input: DSF

The DSF is latched at the falling edge of RAS and CAS. It allows for the selection of several RAM

ports and transfer operating modes. In addition to the conventional multiport DRAM, the special

functions consisting of flash write, block write, load/read color register, and split read/write

transfer can be invoked.

Special Function Output: QSF

QSF is an output signal, which during split register mode indicates which half of the split SAM

is being accessed. QSF "low" indicates that the lower split SAM (0 - 255) is being accessed. QSF

"high" indicates that the upper SAM (256 - 511) is being accessed.

Serial Input/Output: SDQ1 - SDQ8

Serial input/output mode is determined by the most recent read or write transfer cycle. When

a read transfer cycle is performed, the SAM port is in the output mode. When a write transfer

cycle is performed, the SAM port is switched from output mode to input mode.

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