MSM548262-80JS datasheet(32/37 Pages) OKI

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MSM548262

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Block Write:

RAS falling edge --- CAS = TRG = "H", DSF = "L"

CAS falling edge --- DSF = "H"

Block write allows for the data in the color register to be written into 4 consecutive column

address locations, starting from a selected column address in a selected row.

The block write operation can be selectively controlled on an I/O basis, and a column mask

capability is also available. During a block write cycle, the 2 least significant column address

locations (A0C and A1C) are internally controlled, and only the 7 most significant column

addresses (A2C - A8C) are latched at the falling edge of CAS.

1) No mask block write: WE "high" at the falling edge of RAS

The data on 8 DQ pins is all cleared by the data of the color register.

2) Masked block write: WE "low" at the falling edge of RAS

The mask data is the same as that of a RAM write cycle.

SAM PORT OPERATION

Single Register Mode

High speed serial read or write operation can be performed through the SAM port independent

of the RAM port operation, except during read/write transfer cycles.

The preceding transfer operation determines the direction of data flow through the SAM port.

If the preceding transfer is a read transfer, the SAM port is in the output mode. If the preceding

transfer is write transfer, the SAM port is in the input mode.

Serial data can be read out of the SAM after a read transfer has been performed. The data is shifted

out of the SAM starting at any of the 512 bits locations.

The TAP location corresponds to the column address selected at the falling edge of CAS during

the read or write transfer cycle. The SAM registers are configured as a circular data register. The

data is shifted out sequentially. It starts from the selected TAP location at the most significant bit

(511), then wraps around to the least significant bit (0).

Split Register Mode

In split register mode data can be shifted into or out of one half of the SAM, while a split read or

split write transfer is being performed on the other half of the SAM.

Conventional (non split) read, or write transfer cycle must precede any split read or split write

transfers. The split read and write transfers will not change the SAM port mode set by the

preceding conventional transfer operation. In the split register mode, serial data can be shifted

in or out of one of the split SAM registers, starting from any at the 256 TAP locations, excluding

the last address of each split SAM the data is shifted in or out sequentially starting from the

selected TAP location at the most significant bit (255 or 511) of the first split SAM, and then the

SAM pointer moves to the TAP location selected for the second split SAM to shift data in or out

sequentially, starts from this TAP location at the most significant bit (511 or 255), and finally

wraps around to the least significant bit.

255

TAP

256 257

511

TAP

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