ES8155 datasheet(24/33 Pages) EVEREST

24 / 33 page

Everest Semiconductor

ES8155

Version 1.0

3/29/2011

01 – left data = left DAC, right data = left DAC

10 – left data = right DAC, right data = right DAC

11 – left data = right DAC, right data = left DAC

DACLRP

I2S/left justified/right justified case:

0 – L/R normal polarity (default)

Left / Right = High Level / Low Level (Left Justified, Right Justified)

Left / Right = Low Level / High Level (I2S)

1 – L/R invert polarity

Left / Right = Low Level / High Level (Left Justified, Right Justified)

Left / Right = High Level / Low Level (I2S)

DSP mode case:

0 – Mode A, MSB is available on 2

nd SCLK rising edge after LRCK rising edge

1 – Mode B, MSB is available on 1

st SCLK rising edge after LRCK rising edge

DACWL

2:0

Data word length

000 – 24-bit (default)

001 – 20-bit

010 – 18-bit

011 – 16-bit

100 – 32-bit

6.4.2

Bit Name

Bit

Description

MCLKDIV2

0 – chip clock is MCLK (default)

1 – chip clock is MCLK divide by 2

SCLKINV

0 – normal (default)

1 – SCLK inverted

FSMODE

0 – single speed mode (default)

1 – double speed mode

DACMSC

1 – master mode serial port (default)

0 – slave mode serial port

6.4.3

Bit Name

Bit

Description

DACSR

4:0

DAC sample rate, MCLK frequency/LRCK frequency

ES8155 Datasheet(PDF) 24 Page - Suzhou Everest Semiconductor Co. Ltd.

ES8155 Datasheet(HTML) 24 Page - Suzhou Everest Semiconductor Co. Ltd.

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