ES8155 datasheet(28/33 Pages) EVEREST

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Everest Semiconductor

ES8155

Version 1.0

3/29/2011

MCLKSEL

Select internal master clock

0 – from MCLK pin (default)

1 – from PLL (to use PLL, make sure PLLEN=1, PLL_RB=1, otherwise, the setting will

close chip clock)

PLLOUT_DIV2

0 – divide disabled, PLL out clock is vcoout/4 (default)

1 – divide enabled, PLL out clock is vcoout/8

PLL_RB

0 – PLL held in reset (default)

1 – PLL running (if PLLEN=1)

PLL_EN

0 – PLL disabled (default)

1 – PLL enabled

6.6.3

Bit Name

Bit

Description

DITH_MAG

6:4

Reserved

PLL_N

3:0

Integer part of PLL input/output frequency ratio; Use value greater than 5 and less than 13

6.6.4

Bit Name

Bit

Description

PLL_K[21:16]

5:0

Fractional part of PLL input/output frequency ratio (treat as one 22-digital binary number)

6.6.5

Bit Name

Bit

Description

PLL_K[15:8]

7:0

Fractional part of PLL input/output frequency ratio (treat as one 22-digital binary number)

6.6.6

Bit Name

Bit

Description

PLL_K[7:0]

7:0

Fractional part of PLL input/output frequency ratio (treat as one 22-digital binary number)

Digital Audio Interface

The device provides four formats of serial audio data interface to the input of

the DAC through LRCK, SCLK and SDIN pins. The four formats are I

2S, left

justified, right justified and DSP/PCM mode. DAC input DSDIN is sampled by

ES8155 on the rising edge of DSCLK. The relationship of SDATA (SDIN),

SCLK and LRCK with the three formats is shown through Figure 3 to Figure 7.

n-2 n-1

1 SCLK

MSB

LSB

LEFT CHANNEL

n-2 n-1

1 SCLK

MSB

LSB

RIGHT CHANNEL

SDATA

SCLK

LRCK

Figure 3 I

2S Serial Audio Data Format Up To 24-bit

ES8155 Datasheet(PDF) 28 Page - Suzhou Everest Semiconductor Co. Ltd.

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