Z86C34 datasheet(24/70 Pages) ZILOG

24 / 70 page

Z86C34/C35/C36/C44/C45/C46

CMOS Z8® MCUs with ASCI UART

ZiLOG

P R E L I M I N A R Y

DS007601-Z8X0499

PIN FUNCTIONS (Continued)

Port 1 (P17–P10).

Port 1 is an 8-bit, bidirectional, CMOS-

compatible port (Figure 13), with multiplexed Address

(A7–A0) and Data (D7–D0) ports. For the ROM device,

these eight I/O lines are programmed as inputs or outputs,

or can be configured under software control as an Ad-

dress/Data port for interfacing external memory. The input

buffers are Schmitt-triggered and byte-programmed as out-

puts and can be globally programmed as either push-pull

or open-drain. Low-EMI output buffers can be globally pro-

grammed by the software.

Note: Port 1 is not available on the devices in the 28-pin pack-

age, and P01M Register must set Bit D4,D3 as 00. Low-

EMI mode is not supported on the emulator for Port1.

PCON

Port 1 may be placed under handshake control. In this con-

figuration, Port 3, lines P33 and P34 are used as the hand-

shake controls RDY1 and DAV1 (Ready and Data Avail-

able). Memory locations greater than the internal ROM

address are referenced through Port 1, except for Z86C46.

To interface external memory, Port 1 must be programmed

for the multiplexed Address/Data mode. If more than 256

external locations are required, Port 0 outputs the additional

lines.

Port 1 can be placed in the high-impedance state along with

Port 0, AS, DS, and R/W, allowing the Z8 to share common

resources in multiprocessor and DMA applications.

Figure 13. Port 1 Conﬁguration

Open Drain

Out

1.5

2.3 Hysteresis @ VCC = 5.0V

PAD

Auto Latch

(mask option)

≈ 500 KΩ

Port 1

(I/O or AD7–AD0)

Handshake Controls

DAV1 and RDY1

(P33 and P34)

Pull-Up

Transistor Enable

(Mask Option)

Z86C34 Datasheet(PDF) 24 Page - Zilog, Inc.

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