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Z86C34 Datasheet(PDF) 40 Page - Zilog, Inc.

Part # Z86C34
Description  CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY
PDF  70 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86C34 Datasheet(HTML) 40 Page - Zilog, Inc.

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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
40
P R E L I M I N A R Y
DS007601-Z8X0499
FUNCTIONAL DESCRIPTION (Continued)
Stop-Mode Recovery Delay Select (D5).
This bit, if
High, enables the TPOR RESET delay after Stop-Mode Re-
covery. The default configuration of this bit is 1. If the fast
wake up is selected, the Stop-Mode Recovery source must
be kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6).
A 1 in this bit
position indicates that a high level on any one of the recov-
ery sources wakes the Z8 from STOP mode. A 0 indicates
low-level recovery. The default is 0 on POR (Figure 28).
This bit is used for either SMR or SMR2.
Cold or Warm Start (D7).
This bit is set by the device
upon entering STOP mode. A 0 in this bit (cold) indicates
that the device resets by POR/WDT RESET. A 1 in this bit
(warm) indicates that the device awakens by a Stop-Mode
Recovery source.
Note: If the Port 2 pin is configured as an output, this output
level is read by the SMR2 circuitry.
Figure 28. Stop-Mode Recovery Source
P30
P31
P32
P33
P27
Stop-Mode Recovery Edge
Select (SMR)
P33 From Pads
Digital/Analog Mode
Select (P3M)
To P33 Data
Latch and IRQ1
To POR
RESET
SMR
SMR
SMR
D4 D3 D2
0
0
1
0
1
0
0
1
1
D4 D3 D2
1
0
0
D4 D3 D2
1
0
1
MUX
SMR
SMR
D4 D3 D2
1
1
0
D4 D3 D2
1
1
1
P20
P23
P20
P27
SMR2
SMR2
D1 D0
1
1
D1 D0
1
1
P20
P23
P20
P27
SMR D4 D3 D2
0
0
0
V
SMR2 D1 D0
0
0
DD
VDD
Table 13. Stop-Mode Recovery Source
SMR:432
D4
D3
D2
Operation
Description of Action
0
0
0
POR and/or external reset recovery
0
0
1
P30 transition
0
1
0
P31 transition (not in Analog Mode)
0
1
1
P32 transition (not in Analog Mode)
1
0
0
P33 transition (not in Analog Mode)
1
0
1
P27 transition
1
1
0
Logical NOR of P20 through P23
1
1
1
Logical NOR of P20 through P27



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