ADP3419

Rev. A | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADP3419

TOP VIEW

(Not to Scale)

IN

SD

DRVLSD

CROWBAR

VCC

BST

DRVH

SW

GND

DRVL

1

2

3

10

9

8

4

5

6

7

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Function

1

IN

Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin

low turns on the low-side driver; pulling it high turns on the high-side driver.

2

SD

Shutdown Input. When low, this pin disables normal operation, forcing DRVH and DRVL low.

3

DRVLSD

Synchronous Rectifier Shutdown Input. When low, DRVL is forced low; when high, DRVL is enabled and

controlled by IN and by the adaptive overlap protection control circuitry.

4

CROWBAR

Crowbar Input. When high, DRVL is forced high regardless of the high-side MOSFET switch condition.

5

VCC

Input Supply. This pin should be bypassed to GND with a 4.7 µF or larger ceramic capacitor.

6

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

7

GND

Ground. This pin should be closely connected to the source of the lower MOSFET.

8

SW

Switch Node Input. This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is

the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent

turn-on of the lower MOSFET until the voltage is below ~1 V.

9

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

10

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this

bootstrapped voltage for the high-side MOSFET as it is switched.