ISO1432 datasheet(28/47 Pages) TI1

28 / 47 page

ISO1430, ISO1432, ISO1450, ISO1452

ISO1410, ISO1412

SLLSF22C – APRIL 2018 – REVISED APRIL 2019

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Product Folder Links: ISO1430 ISO1432 ISO1450 ISO1452 ISO1410 ISO1412

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Feature Description (continued)

(1)

PU = Powered Up; PD = Powered Down; H = High Level; L = Low level; X = Irrelevant, Hi-Z = High impedance state

(2)

The driver outputs are Y and Z for a full-duplex device. The driver outputs are A and B for a half-duplex device.

(3)

A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined

output.

Bus short circuit for an extended duration and/or beyond voltage levels specified in recommended operating

condition should be avoided. Repeated or prolonged exposure to bus shorts can result in high junction

temperatures and affect device reliability.

10.3.4 Glitch-Free Power Up and Power Down

Communication on the bus that already exist between a master node and slave node in an RS485 network must

not be disturbed when a new node is swapped in or out of the network. No glitches on the bus occur when the

device is:

•

Hot plugged into the network in an unpowered state

•

Hot plugged into the network in a powered state and disabled state

•

Powered up or powered down in a disabled state when already connected to the bus

The ISO14xx devices do not cause any false data toggling on the bus when powered up or powered down in a

disabled state with supply ramp rates from 100 µs to 10 ms.

10.4 Device Functional Modes

Table 2 shows the driver functional modes.

Table 2. Driver Functional table(1)

VCC1

VCC2

INPUT D

DRIVER ENABLE

OUTPUTS(2)

Y, A

Z, B

Hi-Z

Open

Hi-Z

Open

PD(3)

Hi-Z

(1)

PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state

The description that follows is specific to half-duplex device but the same logic applies to full-duplex device with

the outputs being Y and Z.

When the driver enable pin, DE, is logic high, the differential outputs, A and B, follow the logic states at data

input, D. A logic high at the D input causes the A output to go high and the B output to go low. Therefore the

differential output voltage defined by Equation 1 is positive.

VOD = VA – VB

(1)

A logic low at the D input causes the B output to go high and the A output to go low. Therefore the differential

output voltage defined by Equation 1 is negative. A logic low at the DE input causes both outputs to go to the

high-impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin

has an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when

the DE pin is left open. The D pin has an internal pullup resistor. The A output goes high and the B output goes

low when the D pin is left open while the driver enabled.

Table 3 shows the receiver functional modes.

Table 3. Receiver Functional Table(1)

VCC1

VCC2

DIFFERENTIAL INPUT

RECEIVER ENABLE RE

OUTPUT R

VID = VA – VB

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