DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface

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2-WIRE BUS SYSTEM

The 2-Wire bus system supports operation as a slave only device in a single or multi-slave, and single or multi-

master system. Up to 128 slave devices may share the bus by uniquely setting the 7-bit slave address. The 2-wire

interface consists of a serial data line (SDA) and serial clock line (SCL). SDA and SCL provide bidirectional

communication between the DS2764 slave device and a master device at speeds up to 100kHz. The DS2764’s

SDA pin operates bi-directionally, that is, when the DS2764 receives data, SDA operates as an input, and when the

DS2764 returns data, SDA operates as an open drain output, with the host system providing a resistive pull-up.

The DS2764 always operates as a slave device, receiving and transmitting data under the control of a master

device. The master initiates all transactions on the bus and generates the SCL signal as well as the START and

STOP bits which begin and end each transaction.

Bit Transfer

One data bit is transferred during each SCL clock cycle, with the cycle defined by SCL transitioning low-to-high and

then high-to-low. The SDA logic level must remain stable during the high period of the SCL clock pulse. Any

change in SDA when SCL is high is interpreted as a START or STOP control signal.

Bus Idle

The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high

when the bus is idle. The STOP condition is the proper method to return the bus to the idle state.

START and STOP Conditions

The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL

is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL

is high. A Repeated START condition (Sr) can be used in place of a STOP then START sequence to terminate

one transaction and begin another without returning the bus to the idle state. In multi-master systems, a Repeated

START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities

in which the SDA transitions when SCL is high.

Acknowledge Bits

Each byte of a data transfer is acknowledged with an Acknowledge bit (A) or a No Acknowledge bit (N). Both the

master and the DS2764 slave generate acknowledge bits. To generate an Acknowledge, the receiving device

must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until

SCL returns low. To generate a No Acknowledge (also called NAK), the receiver releases SDA before the rising

edge of the acknowledge-related clock pulse and leaves SDA high until SCL returns low.

Monitoring the

acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a

receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus

master should re-attempt communication.

Data Order

A byte of data consists of 8 bits ordered most significant bit (msb) first. The least significant bit (lsb) of each byte is

followed by the Acknowledge bit. DS2764 registers composed of multi-byte values are ordered most significant

byte (MSB) first. The MSB of multi-byte registers is stored on even data memory addresses.

Slave Address

A bus master initiates communication with a slave device by issuing a START condition followed by a Slave

Address (SAddr) and the read/write (R/W) bit. When the bus is idle, the DS2764 continuously monitors for a

START condition followed by its slave address. When the DS2764 receives a slave address that matches the

value in its Programmable Slave Address register, it responds with an Acknowledge bit during the clock period

following the R/W bit. The 7-bit Programmable Slave Address register is factory programmed to 0110100. The

slave address can be re-programmed, refer to the Programmable Slave Address section for details.

Read/Write Bit

The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0

selects a write transaction, with the following bytes being written by the master to the slave. R/W = 1 selects a

read transaction, with the following bytes being read from the stave by the master.