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ADV202 Datasheet(PDF) 13 Page - Analog Devices

Part # ADV202
Description  JPEG2000 Video Codec
PDF  40 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV202 Datasheet(HTML) 13 Page - Analog Devices

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ADV202
Rev. 0 | Page 13 of 40
DREQ
DACK
WEFB
HDATA
WEHI
WELO
tDACKSU
tHD
tSU
0
1
13
14
15
tDREQWAIT
tDREQRTN
Figure 15. Burst Write Cycle for Fly-By DMA Mode
(DREQ Pulse Width Is Programmable)
EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter
Description
Min
Typ
Max
Unit
DREQPULSE
DREQ Pulse Width1
1
15
JCLK cycles2
t
DREQRTN
DACK to DREQ Deassert (DR × PULS = 0)
2.5
3.5 × JCLK + 7.5 ns
JCLK cycles
t
DACK
SU
DACK to RD Setup
0
ns
tRD
DACK to Data Valid
2.5
9.7
ns
tHD
Data Hold
2.5
ns
RDLO
RD Assert Pulse Width
1.5
JCLK cycles
RDHI
RD Deassert Pulse Width
1.5
JCLK cycles
t
DREQWAIT
DACK Deassert to Next DREQ
2.5
3.5 × JCLK + 7.5 ns3
JCLK cycles
1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed.
2 For a definition of JCLK, see the
section.
PLL
3 If sufficient data is available in FIFO.
DREQ
DACK
RD
HDATA
RDHI
RDLO
tDACKSU
tHD
0
1
13
14
15
tDREQWAIT
DREQPULSE
tRD
Figure 16. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0



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