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ADV202 Datasheet(PDF) 16 Page - Analog Devices |
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ADV202 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 40 page ![]() ADV202 Rev. 0 | Page 16 of 40 Parameter Description Min Typ Max Unit FIELDHD FIELD Hold from Rising VCLK 3 ns FIELDTD VCLK to FIELD Valid 12 SYNC DELAY Decode Data Sync Delay for HD Input with EAV/SAV Codes 7 VCLK cycles Decode Data Sync Delay for SD Input with EAV/SAV Codes 9 VCLK cycles Decode Data Sync Delay for DUAL_LANE (Extended) Input 7 VCLK cycles Decode Data Sync Delay for HVF Input (from First Rising VCLK after HSYNC Low to First Data Sample) 10 VCLK cycles Cr Y Cb Y FF EAV FF SAV Cb Y Cr VDATAHD VDATASU VCLK VDATA(IN) ENCODE CCIR-656 LINE VDATATD VCLK VDATA(OUT) VDATA(OUT) Cr Y Cb Y FF EAV FF SAV Cb Y Cr DECODE MASTER CCIR-656 LINE VCLK VDATA(OUT) VDATATD SYNC DELAY Cr Y Y Cb Y FF EAV FF SAV Cb Y *HSYNC AND VSYNC DO NOT HAVE TO BE APPLIED SIMULTANEOUSLY VCLK VDATA(IN) HSYNC VSYNC Cr Y Y Cb Y Cr Y Cb Y Y Cr Y Cb Cb HSYNCSU ENCODE HVF MODE DECODE SLAVE CCIR-656 LINE HSYNCHD VSYNCSU VSYNCHD Cb Y Cr Y Cb Cb Y VCLK HSYNC VSYNC DECODE SLAVE HVF MODE HSYNCHD* VDATATD SYNC DELAY VSYNCHD* Cb Y Cr Y Figure 21. Video Mode Timing |
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