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CS4271 Datasheet(PDF) 21 Page - Cirrus Logic |
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CS4271 Datasheet(HTML) 21 Page - Cirrus Logic |
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21 / 53 page ![]() CS4271 DS592F1 21 SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL) Notes: 21. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Parameter Symbol Min Max Unit I²C Mode SCL Clock Frequency. fscl -100 KHz RST Rising Edge to Start. tirs 500 - ns Bus Free Time Between Transmissions. tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse). thdst 4.0 - µs Clock Low time. tlow 4.7 - µs Clock High Time. thigh 4.0 - µs Setup Time for Repeated Start Condition. tsust 4.7 - µs SDA Hold Time from SCL Falling. (Note 21) thdd 0- µs SDA Setup time to SCL Rising. tsud 250 - ns Rise Time of Both SDA and SCL Lines. tr -1 µs Fall Time of Both SDA and SCL Lines. tf -300 ns Setup Time for Stop Condition. tsusp 4.7 - µs t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp Stop Start Start Stop Repeated SDA SCL t irs RST Figure 6. I²C Mode Control Port Timing |
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