C9827H
High Performance Pentium® 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 5 of 25
Approved Product
Byte 4: DRCG Control Register
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
7
0
-
SS2 Spread Spectrum control bit
(0=down spread, 1=Center spread)
6
0
-
Reserved
5
1
33
3V66_0 Output Enabled
1 = enabled, 0 = disabled
4
1
35
3V66_1/VCH Output Enable
1 = enabled, 0 = disabled
3
1
24
3V66_5 Output Enable
1 = enabled, 0 = disabled
2
1
23
66B2/3V66_4 Output Enabled
1 = enabled, 0 = disabled
1
1
22
66B1/3V66_3 Output Enabled
1 = enabled, 0 = disabled
0
1
21
66B0/3V66_2 Output Enabled
1 = enabled, 0 = disabled
Byte 6: Silicon Signature Register
(all bits are read only)
Bit
@Pup
Pin#
Description
70
-
60
-
50
-
40
-
30
-
20
-
11
-
01
-
Vendor Code
011 = IMI
Note: When writing to this register the device will acknowledge the
write operation, but the data itself will be ignored.
Byte 8: Dial-a-Frequency™ Control Register N
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
70
0
N7, MSB
60
0
N6
50
0
N5
40
0
N4
30
0
N3
20
0
N2
10
0
N3
0
0
0
N0, LSB
66IN to 66M Delay Control Table
Byte5
Bit5
Bit4
Delay (ns)
0
0
4.29
0
1
4.43
1
0
3.95 (default)
1
1
3.95
Byte 5: Clock control register
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
7
0
-
SS1 Spread Spectrum control bit
6
1
-
SS0 Spread Spectrum control bit
5
0
-
66IN to 66M delay Control MSB, See table
4
0
-
66IN to 66M delay Control LSB, See table
3
0
-
Reserved
2
0
-
48MDOT edge rate control. When set to 1,
the edge is slowed by 15%.
1
0
-
Reserved
0
0
-
USB edge rate control. When set to 1, the
edge is slowed by 15%
Byte 7: Watch Dog Time Stamp Register
Bit
@Pup
Pin#
Description
7
0
-
Reserved
6
0
-
Reserved
5
0
-
Reserved
40
-
Reserved
3
0
-
Reserved
2
0
-
Reserved
1
0
-
Reserved
0
0
-
Reserved
Byte 9: Dial-a-Frequency™ Control Register R
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
70
-
R6 MSB
60
-
R5
50
-
R4
40
-
R3
3
0
-R2
2
0
-R1
1
0
-
R0, LSB
0
0
-
R and N register load gate 0=gate closed
(data is latched), 1=gate open (data is
loading from SMBus registers into R and
N)
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