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C9827H
High Performance Pentium® 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 20 of 25
Approved Product
PD# - De-assertion (transition from logic ‘0’ to logic ‘1’)
The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 mS.
CPU 133MHz
3V66
CPU# 133MHz
REF 14.318MHz
USB 48MHz
PCIF / APIC
33MHz
66In
66Buff[0,2]
PWRDWN#
66Buff1 / GMCH
100uS max
<3mS
PCI 33MHz
30uS min
Power Down De-Assertion Timing Waveforms Figure
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