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C9827H
High Performance Pentium® 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 16 of 25
Approved Product
CPU_STP# - Assertion (transition from logic ‘1’ to logic ‘0’)
When CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via
assertion of CPU_STP# will be stopped after being sampled by 2 falling CPU clock edges. The final state of the
stopped CPU signals is CPU = high and CPU0# = Low. There is no change to the output drive current values during
the stopped state. The CPU is driven high with a current value equal to (Mult 0 ‘select’) x (Iref), and the CPU# signal
will not be driven. Due to external pulldown circuitry CPU# will be low during this stopped state.
CPU_STP#
CPU
CPU#
Assertion CPU_STP# Waveform Figure
CPU_STP# Functionality Table
CPU_STP#
CPU#4
CPU
DRCG
66CLK(0:2)
PCI_F/PCI
PCI
USB/DOT
1
Normal
Normal
66M
66Input
66Input/2
66Input/2
48M
0
Iref*Mult
Float
66M
66Input
66Input/2
66Input/2
48M
CPU_STP# De-assertion (transition from logic ‘0’ to logic ‘1’)
The de-assertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation
in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produces
when the clock resumes. The maximum latency from the de-assertion to active outputs is no more than 2 CPU clock
cycles.
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