AD9176 datasheet(2/151 Pages) AD

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AD9176

Data Sheet

Rev. A | Page 2 of 151

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

Digital Specifications ................................................................... 5

Maximum DAC Sampling Rate Specifications......................... 5

Power Supply DC Specifications ................................................ 6

Serial Port and CMOS Pin Specifications ................................. 9

Digital Input Data Timing Specifications ............................... 10

JESD204B Interface Electrical and Speed Specifications ...... 11

Input Data Rates and Signal Bandwidth Specifications ........ 12

AC Specifications........................................................................ 13

Absolute Maximum Ratings.......................................................... 15

Reflow Profile.............................................................................. 15

Thermal Characteristics ............................................................ 15

ESD Caution................................................................................ 15

Pin Configuration and Function Descriptions........................... 16

Typical Performance Characteristics ........................................... 19

Terminology .................................................................................... 27

Theory of Operation ...................................................................... 28

Serial Port Operation ..................................................................... 30

Data Format ................................................................................ 30

Serial Port Pin Descriptions...................................................... 30

Serial Port Options..................................................................... 31

JESD204B Serial Data Interface.................................................... 32

JESD204B Overview .................................................................. 32

Physical Layer ............................................................................. 36

Data Link Layer .......................................................................... 38

Syncing LMFC Signals............................................................... 40

Transport Layer .......................................................................... 46

JESD204B Test Modes ............................................................... 47

JESD204B Error Monitoring..................................................... 49

Digital Datapath ............................................................................. 52

Total Datapath Interpolation .................................................... 52

Channel Digital Datapath ......................................................... 53

Main Digital Datapath............................................................... 56

NCO Only Mode........................................................................ 60

Modulator Switch....................................................................... 61

Interrupt Request Operation ........................................................ 65

Interrupt Service Routine.......................................................... 65

Analog Interface ............................................................................. 66

DAC Input Clock Configurations............................................ 66

Clock Output Driver.................................................................. 68

Analog Outputs .......................................................................... 68

Applications Information .............................................................. 70

Hardware Considerations ......................................................... 70

Start-Up Sequence.......................................................................... 73

Outline Dimensions..................................................................... 151

Ordering Guide ........................................................................ 151

REVISION HISTORY

5/2019—Rev. 0 to Rev. A

Changes to General Description Section ...................................... 1

Change to Table 8 ........................................................................... 12

Changes to Table 9.......................................................................... 14

Change to Figure 16 Caption ........................................................ 21

Changes to Figure 17 Caption....................................................... 21

Changes to Table 17........................................................................ 33

Changes to SYSREF± Sampling Section...................................... 41

Changes to Subclass 1 Section ...................................................... 42

Change to Table 37 ......................................................................... 54

Change to Complex Modulator Switch Configuration

Section.............................................................................................. 63

Changes to DAC On-Chip PLL Section...................................... 67

Changes to Table 51 ....................................................................... 73

Changes to Table 60 ....................................................................... 80

Changes to Table 61 ....................................................................... 88

11/2018—Revision 0: Initial Version

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